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w25q32fv publication release date: june 03, 2016 revision j 3v 32 m - bit serial flash memory with dual / quad spi & qpi
w25q32fv - 1 - table of contents 1. general descriptions ................................ ................................ ................................ ............. 5 2. featu res ................................ ................................ ................................ ................................ ....... 5 3. package types and pi n configurations ................................ ................................ ........... 6 3.1 pin configuration soic 208 - mil / vsop 208 - mil ................................ ................................ .. 6 3.2 pad configuration wson 6x5 - mm / 8x6 - mm ................................ ................................ ...... 6 3.3 pin description soic / vsop 208 - mil, wson 6x5 - mm / 8x6 - mm ................................ ...... 6 3.4 pin configuration soic 300 - mil ................................ ................................ ........................... 7 3.5 pin description soic 300 - mil ................................ ................................ ............................... 7 3.6 ball configuration tfbga 8x6 - mm (5x 5 or 6x4 ball array) ................................ ................. 8 3.7 ball description tfbga 8x6 - mm ................................ ................................ ......................... 8 3.8 pin configuration pdip 300 - mil ................................ ................................ ............................ 9 3.9 pin description pdip 300 - mil ................................ ................................ ............................... 9 4. pin descriptions ................................ ................................ ................................ ...................... 10 4.1 chip select (/cs) ................................ ................................ ................................ ................ 10 4.2 serial data input, output and ios (di, do and io0, io1, io2, io3) ................................ ... 10 4.3 write protect (/wp) ................................ ................................ ................................ ............ 10 4.4 hold (/hold) ................................ ................................ ................................ ................... 10 4.5 serial clock (clk) ................................ ................................ ................................ .............. 10 4.6 reset (/reset) ................................ ................................ ................................ .................. 10 5. block diagram ................................ ................................ ................................ .......................... 11 6. functional descripti ons ................................ ................................ ................................ ..... 12 6.1 spi / qpi operations ................................ ................................ ................................ .......... 12 6.1.1 standard spi instructions ................................ ................................ ................................ .... 12 6.1.2 dual spi instructions ................................ ................................ ................................ ............ 12 6.1.3 quad spi instru ctions ................................ ................................ ................................ .......... 13 6.1.4 qpi instructions ................................ ................................ ................................ .................... 13 6.1.5 hold function ................................ ................................ ................................ ....................... 13 6.1.6 software reset & hardware /reset pin ................................ ................................ ............. 14 6.2 write protection ................................ ................................ ................................ .................. 15 6.2.1 write protect features ................................ ................................ ................................ ......... 15 7. status and configura tion registers ................................ ................................ ............ 16 7.1 status registers ................................ ................................ ................................ ................. 16 7.1.1 erase/write in progress (busy) C status only ................................ ................................ ... 16 7.1.2 write enable latch (wel) C status only ................................ ................................ ............. 16 7.1.3 block protect bits (bp2, bp1, bp0) C volatile/non - volatile writable ................................ ... 16
w25q32fv publication release date: june 03, 2016 - 2 - revision j 7.1.4 top/bottom block protect (tb) C volatile/non - volatile writable ................................ .......... 17 7.1.5 sector/block protect bit (sec ) C volatile/non - volatile writable ................................ .......... 17 7.1.6 complement protect (cmp) C volatile/non - volatile writable ................................ ............... 17 7.1.7 status register p rotect (srp 1, srp0 ) C volatile/non - volatile writable .............................. 17 7.1.8 erase/program suspend status (sus) C status only ................................ ......................... 18 7.1.9 security register lock bits (lb3, lb2, lb1) C volatile/non - volatile otp writable ............. 18 7.1.10 quad enable ( qe ) C volatile/non - volatile writable ................................ ........................... 18 7.1.11 write protect selection (wps) C volatile/non - volatile writable ................................ ........ 19 7.1.12 output driver strength (drv1, drv0) C volatile/non - volatile writable ............................ 19 7.1.13 hold or /reset pin function (hold/rst) C volatile/non - volatile writable .................. 19 7.1.14 reserved bits C non functional ................................ ................................ ......................... 20 7.1.15 w25q32fv status register memory protection (wps = 0, cmp = 0) .............................. 21 7.1.16 w25q32fv status register memory protection (wps = 0, cmp = 1) .............................. 22 7.1.17 w25q32fv individual block memory protection (wps=1) ................................ ............... 23 8. instructions ................................ ................................ ................................ ............................. 24 8.1 device id and instruction set tables ................................ ................................ ................. 24 8.1.1 manufacturer and device identification ................................ ................................ ................ 24 8.1.2 instruction set table 1 (standard/ dual/quad spi instructions) (1) ................................ ........ 25 8.1.3 instruction set table 2 (standard/dual/quad spi instructions) (1) ................................ ........ 26 8.1.4 instruction se t table 3 (qpi instructions) (14) ................................ ................................ ........ 27 8.2 instruction descriptions ................................ ................................ ................................ ...... 29 8.2.1 write enable (06h) ................................ ................................ ................................ ............... 29 8.2.2 write enable for volatile status register (50h) ................................ ................................ ... 29 8.2.3 write disable (04h) ................................ ................................ ................................ .............. 30 8.2.4 read status register - 1 (05h), status register - 2 ( 3 5h) & status register - 3 (15h) .............. 30 8.2.5 write status register - 1 (01h), status register - 2 ( 3 1h) & status register - 3 (11h) .............. 31 8.2.6 read data (03h) ................................ ................................ ................................ ................... 34 8.2.7 fast read (0bh) ................................ ................................ ................................ ................... 35 8.2.8 fast read dual output (3bh) ................................ ................................ ............................... 37 8.2.9 fast read quad output (6bh) ................................ ................................ ............................. 38 8.2.10 f ast read dual i/o (bbh) ................................ ................................ ................................ .. 39 8.2.11 fast read quad i/o (ebh) ................................ ................................ ................................ . 41 8.2.12 word read quad i/o (e7h) ................................ ................................ ................................ 44 8.2.13 octal word read quad i/o (e3h) ................................ ................................ ...................... 46 8.2.14 set burst with wrap (77h) ................................ ................................ ................................ .. 48 8.2.15 page program (02h) ................................ ................................ ................................ ........... 49 8.2.16 q uad input page program ( 3 2h) ................................ ................................ ........................ 51 8.2.17 sector erase (20h) ................................ ................................ ................................ ............. 52 8.2.18 32kb block erase (52h) ................................ ................................ ................................ ..... 53 8.2.19 64kb block erase (d8h) ................................ ................................ ................................ .... 54 8.2.20 chip erase (c7h / 60h ) ................................ ................................ ................................ ...... 55
w25q32fv - 3 - 8.2.21 erase / program suspend ( 75h) ................................ ................................ ........................ 56 8.2.22 erase / program resume (7ah) ................................ ................................ ......................... 58 8.2.23 power - down (b9h) ................................ ................................ ................................ .............. 59 8.2.24 release power - down / device id (abh) ................................ ................................ ............. 60 8.2.25 read manufacturer / device id (90h) ................................ ................................ ................. 62 8.2.26 read manufacturer / device id dual i/o (92h) ................................ ................................ .. 63 8.2.27 read manufacturer / device id quad i/o (94h) ................................ ................................ . 64 8.2.28 read unique id number (4bh) ................................ ................................ .......................... 65 8.2.29 read jedec id (9fh) ................................ ................................ ................................ ........ 66 8.2.30 read sfdp register (5ah) ................................ ................................ ................................ 67 8.2. 31 erase security registers (44h) ................................ ................................ .......................... 68 8.2.32 program security registers (42h) ................................ ................................ ...................... 69 8.2.33 read security registers (48h) ................................ ................................ ........................... 70 8.2.34 set read parameters (c0h) ................................ ................................ ............................... 71 8.2.35 burst read with wrap (0ch) ................................ ................................ .............................. 72 8.2.36 enter qpi mode (38h) ................................ ................................ ................................ ........ 73 8.2.37 exit qpi mode (ffh) ................................ ................................ ................................ .......... 74 8.2.38 individual block/sector lock (36h) ................................ ................................ ..................... 75 8.2.39 individual block/sector unlock (39h) ................................ ................................ ................. 76 8.2.40 read block/sector lock (3dh) ................................ ................................ ........................... 77 8.2.41 global block/sector lock (7eh) ................................ ................................ ......................... 78 8.2.42 global block/sector unlock (98h) ................................ ................................ ...................... 78 8.2.43 enable reset (66h) and reset device (99h) ................................ ................................ ...... 79 9. electrical character istics ................................ ................................ ............................... 80 9.1 absolute maximum ratings (1) (2) ................................ ................................ ................... 80 9.2 operating ranges ................................ ................................ ................................ ............... 80 9.3 power - up power - down timing and requirements ( 1 ) ................................ ....................... 81 9.4 dc electrical characteristic s ( 1 ) ................................ ................................ .......................... 82 9.5 ac measurement conditions ( 1 ) ................................ ................................ ......................... 83 9.6 ac electrical characteristics (6) ................................ ................................ ........................... 84 9.7 serial output timing ................................ ................................ ................................ ........... 86 9.8 serial input timing ................................ ................................ ................................ .............. 86 9.9 hold timing ................................ ................................ ................................ ...................... 86 9.10 wp timing ................................ ................................ ................................ .......................... 86 10. package specificatio ns ................................ ................................ ................................ ........ 87 10.1 8 - pin soic 208 - mil (package code ss) ................................ ................................ ............ 87 10.2 8 - pin vsop 208 - mil (package code st) ................................ ................................ ........... 88 10.3 8 - pad wson 6x5 - mm (package code zp) ................................ ................................ ....... 89 10.4 8 - pad wson 8x6 - mm (package code ze) ................................ ................................ ....... 90
w25q32fv publication release date: june 03, 2016 - 4 - revision j 10.5 16 - pin soic 300 - mil (package code sf) ................................ ................................ .......... 91 10.6 8 - pin pdip 30 0 - mil (package code da) ................................ ................................ ............ 92 10.7 24 - ball tfbga 8x6 - mm (package code tb, 5x5 - 1 ball array) ................................ .......... 93 10.8 24 - ball tfbga 8x6 - mm (package c ode tc, 6x4 ball array) ................................ ............. 94 11. ordering information ................................ ................................ ................................ .......... 95 11.1 valid part numbers and top side marking ................................ ................................ ........ 96 12. revision history ................................ ................................ ................................ ...................... 97
w25q32fv - 5 - 1. general description s the w 25q32fv ( 32m - bit) serial flash memory provide s a storage solution for systems with limited space, pins and power. the 25 q series offe rs flexibility and performance well beyond ordinary serial flash devices. they are ideal for code shadowing to ram, executing code directly from d ua l/quad spi (xip ) and storing voice, text and data. the device operate s on a single 2.7 v to 3.6 v power supply with current consumption as low as 4 ma active and 1a for power - down. all devices are of fered in space - saving packages. the w 25q32fv array is organized into 16 , 384 programmable pages of 256 - bytes each. up to 256 bytes can be programmed at a time. pages ca n be erased in groups of 16 ( 4kb sector erase), groups of 128 (32kb block erase), groups of 256 ( 64kb block erase) or the entire chip (chip erase). the w 25q32fv has 1,024 erasable sectors and 64 erasable blocks respectively. the small 4kb sectors allow for greater flexibility in applications that require data and parameter storage. (see figure 2.) the w 25q32fv support the standard serial peripheral interface (spi), dual/quad i/o spi as well as 2 - clocks instruction cycle quad peripheral interface (qpi) : ser ial clock, chip select, serial data i/o 0 (di), i/o1 (do), i/o2 (/wp), and i/o3 (/hold) . spi clock frequencies of up to 104 mhz are supported allowing equivalent clock rates of 208 mhz ( 104 mhz x 2) for dual i/o and 416 mhz ( 104 mhz x 4) for quad i/o when using the fast read dual/quad i/o and qpi instructions. these transfer rates can outperform standard asynchronous 8 and 16 - bit parallel flash memories. the continuous read mode allows for efficient memory access with as few as 8 - clocks of instruction - overhead to read a 24 - bit address, allowing true xip ( execute in place) operation. a hold pin, write protect pin and programmable write protect ion, with top or bottom array control , provide further control flexibility. additionally, the device supports jedec standar d manufacturer and device id and sfdp register , a 64 - bit unique serial number and three 256 - bytes security registers . 2. features ? new family of spiflash memories C w 25q32fv : 32m - bit / 4 m - byte C standard spi: clk, /cs, di, do, /wp, /hold C dual spi: clk, /cs, io 0 , io 1 , /wp, /hold C quad spi: clk, /cs, io 0 , io 1 , io 2 , io 3 C qpi: clk, /cs, io 0 , io 1 , io 2 , io 3 C software & hardware reset ? highest performance serial flash C 104 mhz single, dual/quad spi clocks C 208 / 416 mhz equivalent dual/quad spi C 5 0mb/s continuous data transfer rate C more than 100,000 erase/program cycles C more than 20 - year data retention ? efficient continuous read and qpi mode C continuous read with 8/16/32/64 - byte wrap C as few as 8 clocks to address memory C quad peripheral interface (qpi) red uces instruction overhead C allows true xip (execute in place) operation C outperforms x16 parallel flash ? low power, wide temperature range C single 2.7 to 3.6v supply C 4ma active current, <1a power - down (typ.) C - 40c to +85c operating range ? flexible architecture with 4kb sectors C uniform sector/block erase (4k/32k/64k - byte ) C program 1 to 256 byte per programmable page C erase/program suspend & resume ? advanced security features C software and hardware write - protect C power supply lock - down and otp pr otection C top/bottom, c omplement array protection C individual block/sector array protection C 64 - bit unique id for each device C discoverable parameters (sfdp) register C 3 x256 - bytes security registers with otp locks C volatile & non - volatile status regi ster bits ? space efficient packaging C 8 - pin soic 208 - mil / vsop 208 - mil C 8 - pad wson 6x5 - mm / 8x6 - mm C 16 - pin soic 300 - mil (additional /reset pin) C 8 - pin pdip 300 - mil C 24 - ball tfbga 8x6 - mm (6x4/5x5 ball array) C contact winbond for kgd and other options
w25q32fv publication release date: june 03, 2016 - 6 - revision j 3. package types and pi n configurations 3.1 pin configuration soic 208 - mil / vsop 208 - mil figure 1a. w 25q32fv pin assignments, 8 - pin soic / vsop 208 - mil (package code s s / st ) 3.2 pad configuration wson 6x5 - mm / 8x6 - mm figure 1 b . w 25 q32fv pad assignments, 8 - pad wson 6x5 - mm / 8x6 - mm (package code zp / z e) 3.3 p in description soic / vsop 208 - mil, wson 6x5 - mm / 8x6 - mm pin no. p in name i/o function 1 /cs i chip select input 2 do (io1) i/ o data output ( data input output 1) (1) 3 /wp (io2) i / o write protect input ( data input output 2) (2) 4 gnd ground 5 di (io0) i/o data input ( data input output 0) (1) 6 clk i serial clock input 7 /hold or /reset (io3) i /o hold or reset input (data input output 3) (2) 8 vcc power supply notes: 1. io0 an d io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions , /wp & /hold (or /reset) functions are only available for standard/dual spi. 1 2 3 4 8 7 6 5 / c s d o ( i o 1 ) / w p ( i o 2 ) g n d v c c / h o l d o r / r e s e t ( i o 3 ) d i ( i o 0 ) c l k t o p v i e w 1 2 3 4 / c s d o ( i o 1 ) / w p ( i o 2 ) g n d v c c / h o l d o r / r e s e t ( i o 3 ) d i ( i o 0 ) c l k t o p v i e w 8 7 6 5
w25q32fv - 7 - 3.4 pin configuration soic 300 - mil figure 1 c . w 25q32fv pin assignments, 16 - p in soic 300 - mil (package code s f) 3.5 pin description soic 300 - mil pin no. pin name i/o function 1 /hold (io3) i /o hold input (data input output 3) (2) 2 vcc power supply 3 /reset i reset input (3) 4 n/c no connect 5 n/c no connect 6 n/c no connect 7 /cs i chip select input 8 do (io1) i/ o data output (data input output 1) (1) 9 /wp (io2) i /o write protect input (data input output 2) (2) 10 gnd ground 11 n/c no connect 12 n/c no connect 13 n/c no connect 14 n/c no connect 15 di (io0) i /o data input (data input output 0) (1) 16 clk i serial clock input notes: 1. io0 and io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions, /wp & /hold (or /reset) functions are only available for standard/dual sp i. 3. the /reset pin on soic - 16 package is independent of the hold/rst bit and qe bit settings in the status register. this pin can be left floating , if r est function is not needed . 1 2 3 4 / c s d o ( i o 1 ) / w p ( i o 2 ) g n d v c c / h o l d ( i o 3 ) d i ( i o 0 ) c l k t o p v i e w n c / r e s e t n c n c n c n c n c n c 5 6 7 8 1 0 9 1 1 1 2 1 3 1 4 1 5 1 6
w25q32fv publication release date: june 03, 2016 - 8 - revision j 3.6 ball configuration tfbga 8x6 - mm (5x5 or 6x4 ball array) figure 1 d . w 25 q32fv ball assignments, 24 - ball tfbga 8x6 - mm (package code t b & t c ) 3.7 ball description tfbga 8x6 - mm ball no. pin name i/o function b2 clk i serial clock input b3 gnd ground b4 vcc power supply c2 /cs i chip select input c4 /wp (io2) i /o write protect input (data input output 2) (2) d2 do (io1) i/ o data output (data input output 1) (1) d3 di (io0) i /o data input (data input output 0) (1) d4 /hold or /reset (io3) i /o hold or reset input (data input output 3) (2) multiple nc no connect notes: 1. io0 an d io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions, /wp & /hold (or /reset) functions are only available for standard/dual spi. d 1 / h o l d ( i o 3 ) / r e s e t d i ( i o 0 ) d o ( i o 1 ) / w p ( i o 2 ) d 2 d 3 d 4 n c e 1 n c n c n c e 2 e 3 e 4 n c f 1 n c n c n c f 2 f 3 f 4 n c a 1 n c n c n c a 2 a 3 a 4 n c b 1 v c c g n d c l k b 2 b 3 b 4 n c c 1 n c / c s c 2 c 3 c 4 n c t o p v i e w p a c k a g e c o d e t c d 1 / h o l d ( i o 3 ) / r e s e t d i ( i o 0 ) d o ( i o 1 ) / w p ( i o 2 ) d 2 d 3 d 4 n c e 1 n c n c n c e 2 e 3 e 4 n c b 5 n c n c n c a 2 a 3 a 4 n c b 1 v c c g n d c l k b 2 b 3 b 4 n c c 1 n c / c s c 2 c 3 c 4 n c t o p v i e w p a c k a g e c o d e t b c 5 n c d 5 n c e 5 n c a 5 n c
w25q32fv - 9 - 3.8 pin configuration pdip 300 - mil figure 1 e . w25 q 32fv pin assignments, 8 - pin pdip (package code da) 3.9 pin description pdip 300 - mil pin no. pin name i/o function 1 /cs i chip select input 2 do ( io1 ) i/ o data output ( data input output 1) (1) 3 /wp ( io2 ) i /o write protect input ( data input output 2) (2) 4 gnd ground 5 di ( io0 ) i/o data input ( data input output 0) (1) 6 clk i serial clock input 7 /hold or /reset (io3) i /o hold or reset input (data input output 3) (2) 8 vcc power supply notes: 1. io0 and io1 are used for standard and dual spi instructio ns 2. io0 C io3 are used for quad spi instructions, /wp & /hold (or /reset) functions are only available for standard/dual spi. 1 2 3 4 8 7 6 5 / c s d o ( i o 1 ) / w p ( i o 2 ) g n d v c c / h o l d o r / r e s e t ( i o 3 ) d i ( i o 0 ) c l k t o p v i e w
w25q32fv publication release date: june 03, 2016 - 10 - revision j 4. pin descriptions 4.1 chip select (/cs) the spi chip select (/cs) pin enables and disables device operation. when /cs is high the d evice is deselected and the serial data output (do, or io0, io1, io2, io3) pins are at high impedance. when deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. when /cs is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power - up, /cs must transition from high to low before a new instruction will be a ccepted. the /cs input must track the vcc supply level at power - up and power - down (see write protection and figure 5 8). if needed a pull - up resister on the /cs pin can be used to accomplish this. 4.2 serial data input, output and ios (di, do and io0, io1, io 2, io3) the w 25q32fv supports standard spi, dual spi and quad spi operation. standard spi instructions use the unidirectional di (input) pin to serially write instructions, addresses or data to the device on the rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to read data or status from the device on the falling edge of clk. dual and quad spi instructions use the bidirectional io pins to serially write instructions, addresses or data to the device on the rising edge of clk and read data or status from the device on the falling edge of clk. quad spi instructions require the non - volatile quad enable bit (qe) in status register - 2 to be set. when qe=1, the /wp pin becomes io2 and /hold pin becomes io3. 4.3 w rite protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status registers block protect (cmp, sec, tb, bp2, bp1 and bp0) bits and status register protect (srp) bits, a porti on as small as a 4kb sector or the entire memory array can be hardware protected. the /wp pin is active low. when the qe bit of status register - 2 is set for quad i/o, the /wp pin function is not available since this pin is used for io2. see figure 1a - c for the pin configuration of quad i/o operation. 4.4 hold (/hold) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and signals on the di and clk pins will be ignored (dont care). when /hold is brought high, device operation can resume. the /hold function can be useful when multiple devices are sharing the same spi signals. the /hold pin is active low. when the qe bit of status register - 2 is set for quad i/ o, the /hold pin function is not available since this pin is used for io3. see figure 1a - e for the pin configuration of quad i/o operation. 4.5 serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input and output operations. ("see spi operations") 4.6 reset (/reset) the /reset pin allows the device to be reset by the controller. for 8 - pin packages, when qe=0, the io3 pin can be configured either as a /hold pin or as a /reset pin depending on status register setting. when qe=1, the /hold or /reset function is not available for 8 - pin configuration. on the 16 - pin soic package, a dedicated /reset pin is provided and it is independent of qe bit setting.
w25q32fv - 11 - 5. block diagram figure 2. w 25q3 2fv serial flash memory block diagram 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh column decode and 256 - byte page buffer beginning page address ending page address w25q32fv spi command & control logic byte address latch / counter status register write control logic page address latch / counter do (io 1 ) di (io 0 ) /cs clk /wp (io 2 ) high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data security register 1 - 3 write protect logic and row decode 000000h 0000ffh sfdp register 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 0fff00h 0fffffh ? block 15 (64kb) ? 0f0000h 0f00ffh 10ff00h 10ffffh ? block 16 (64kb) ? 100000h 1000ffh ? ? ? 1fff00h 1fffffh ? block 31 (64kb) ? 1f0000h 1f00ffh 20ff00h 20ffffh ? block 32 (64kb) ? 200000h 2000ffh ? ? ? 3fff00h 3fffffh ? block 63 (64kb) ? 3f0000h 3f00ffh /hold (io 3 ) or /reset (io 3 )
w25q32fv publication release date: june 03, 2016 - 12 - revision j 6. functional descripti on s 6.1 spi / qpi o perations figure 3. w 25q32fv serial flash memory operation diagram 6.1.1 standard spi instructions the w 25q32fv is accessed through an spi compatible bus cons isting of four signals: serial clock (clk), chip select ( /cs ), serial data input ( di ) and serial data output (do). standard spi instructions use the di input pin to serially write instructions, addresses or data to the device on the rising edge of clk . the do output pin is used to read data or status from the device on the falling edge of clk. spi bus operation mode 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi b us master is in standby and data is not being transferred to the serial flash. for mode 0 , the clk signal is normally low on the falling and rising edges of /cs. for mode 3 , the clk signal is normally high on the falling and rising edges of /cs . 6.1.2 dual spi instructions the w 25q32fv support s dual spi operation when using instructions such as fast read dual output (3bh) and fast read dual i/o (bbh) . th ese instructions allow data to be transferred to or from the device at two to three times the rate of ord inary serial flash devices. the dual spi read i nstruction s are ideal for quickly downloading code to ram upon power - up (code - shadowing) or for execut ing non - speed - critical code directly from the spi bus (xip) . when using dual spi instructions , the di and d o pins become bidirectional i/ o pins: io0 and io1. p o w e r u p s t a n d a r d s p i d u a l s p i q u a d s p i q p i e n a b l e q p i ( 3 8 h ) d i s a b l e q p i ( f f h ) s p i r e s e t ( 6 6 h + 9 9 h ) q p i r e s e t ( 6 6 h + 9 9 h ) d e v i c e i n i t i a l i z a t i o n & s t a t u s r e g i s t e r r e f r e s h ( n o n - v o l a t i l e c e l l s ) h a r d w a r e r e s e t h a r d w a r e r e s e t
w25q32fv - 13 - 6.1.3 quad spi instructions the w 25q32fv supports quad spi operation whe n using instructions such as fast read quad output (6bh) , fast read quad i/o (ebh) , word read quad i/o (e7h) and octal word read qua d i/o (e3h) . these instructions allow data to be transferred to or from the device four to six times the rate of ordinary serial flash. the quad read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code - shadowing to ram or execution directly from the spi bus (xip) . when using quad spi instructions the di and do pins become bidirectional io0 and io1 , and the /wp and /hold pins become io2 and io3 respectively. quad spi instructions require the non - vol atile quad enable bit (qe) in status register - 2 to be set . 6.1.4 qpi instructions the w 25q32fv supports quad peripheral interface (qpi) operations only when the device is switched from standard/dual/quad spi mode to qpi mode using the enter qpi (38h) instructi on. the typical spi protocol requires that the byte - long instruction code being shifted into the device only via di pin in eight serial clocks. the qpi mode utilizes all four io pins to input the instruction code, thus only two serial clocks are required. this can significantly reduce the spi instruction overhead and improve system performance in an xip environment. standard/dual/quad spi mode and qpi mode are exclusive. only one mode can be active at any given time. enter qpi (38h) and exit qpi (ffh) i nstructions are used to switch between these two modes. upon power - up or after a software reset using reset (99h) instruction , the default state of the device is standard/dual/quad spi mode. to enable qpi mode, the non - volatile quad enable bit (qe) in st atus register - 2 is required to be set. when using qpi instructions, the di and do pins become bidirectional io0 and io1, and the /wp and /hold pins become io2 and io3 respectively. see figure 3 for the device operation modes. 6.1.5 hold function for standard spi and dual spi operations, t he /hold signal allows the w 25q32fv operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases where the spi data and clock signals are shared with other devices. for example , consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the /hold function can save the state of the instruction and the data in the buffer so programming can resume where it left off onc e the bus is available again. the /hold function is only available for standard spi and dual spi operation, not during quad spi or qpi . the quad enable bit qe in status register - 2 is used to determine if the pin is used as /hold pin or data i/o pin. when q e=0 (factory default), the pin is /hold, when qe=1, the pin will become an i/o pin, /hold function is no longer available. to initiate a /hold condition, the device must be selected with /cs low. a /hold condition will activate on the falling edge of the / hold signal if the clk signal is already low. if the clk is not already low the /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (do) is high impedance, a nd serial data input (di ) and serial clock (clk) are ignored. the chip select ( /cs ) signal should be kept active (low) for the full duration of the /hold operation to avoid resetting the internal logic state of the device.
w25q32fv publication release date: june 03, 2016 - 14 - revision j 6.1.6 software reset & hardware / reset pin the w25q 32 fv can be reset to the initial power - on state by a software reset se quence, either in spi mode or qpi mode. this sequence must include two consecutive commands: enable reset (66h) & reset (99h). if the command sequence is successfully accepted, the device will take approximately 30us ( t rst ) to reset. no command will be acc epted during the reset period. for the wson - 8 and tfbga package types, w25q 32 fv can also be configured to utilize a hardware /reset pin. the hold/rst bit in the status register - 3 is the configuration bit for /hold pin function or reset pin function. when h old/rst=0 (factory default), the pin acts as a /hold pin as described above; when hold/rst=1, the pin acts as a /reset pin. drive the /reset pin low for a minimum period of ~1us (treset*) will reset the device to its initial power - on state. any on - going pr ogram/erase operation will be interrupted and data corruption may happen. while /reset is low, the device will not accept any command input. if qe bit is set to 1, the /hold or /reset function will be disabled, the pin will become one of the four data i/o pins. for the soic - 16 package, w25q 32 fv provides a dedicated /reset pin in addition to the /hold (io 3 ) pin as illustrated in figure 1b. drive the /reset pin low for a minimum period of ~1us (treset*) will reset the device to its initial power - on state. th e hold/rst bit or qe bit in the status register will not affect the function of this dedicated /reset pin. hardware /reset pin has the highest priority among all the input signals. drive /reset low for a minimum period of ~1us (treset*) will interrupt any on - going external/internal operations, regardless the status of other spi signals (/cs, clk, ios, /wp and/or /hold). note: 1. while a faster /reset pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to ensure reliable operation. 2. there is an internal pull - up resistor for the dedicated /reset pin on the soic - 16 package. if the reset function is not needed, this pin can be left floating in the system .
w25q32fv - 15 - 6.2 w rite p rotection applications that use non - volatil e memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern , the w 25q32fv provides several means to protect the data from inadvertent writes. 6.2.1 write protect f eatures ? device resets when vcc is below threshold ? time delay write disable after power - up ? write enable/disable instructions and a ut omatic write disable after e rase or program ? software and hardware (/wp pin) write p r otection using status registers ? additiona l individual block/sector locks for array protection ? write protection using power - down instruction ? lock down write protection for status register until the next power - up ? one time program (otp) write protection for array and security register s using status register * * note : this feature is available upon special order. please contact winbond for details. upon power - up or at power - down , the w 25q32fv will maintain a reset condition while vcc is below the threshold value of v wi , (see power - up timing and volta ge levels and figure 43 ). while reset, all operations are disabled and no instructions are recognized. during power - up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this inc ludes the write enable, page program, sector erase, block erase, chip erase and the write status register instructions. note that the chip select pin ( /cs ) must track the vcc supply level at power - up until the vcc - min level and t vsl time delay is reached , and it must also track the vcc supply level at power - down to prevent adverse command sequence . if needed a pull - up resister on /cs can be used to accomplish this . after power - up the device is automatically placed in a write - disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program, sector erase, block erase, chip erase or write status register instruction will be accepted. after completing a program, erase or write instructi on the write enable latch (wel) is automatically cleared to a write - disabled state of 0. software controlled write protection is facilitated using the write status register instruction and setting the status register protect (srp 0, srp1 ) and block protect ( cmp , sec, tb, bp [ 2 :0] ) bits. these settings allow a portion or the entire memory array to be configured as read only. used in conjunction with the write protect ( /wp ) pin, changes to the status register can be enabled or disabled under hardware control. s ee status register section for further information. additionally, the power - down instruction offers an extra level of write protection as all instructions are ignored except for the release power - down instruction. the w 25q32fv also provides another write p rotect method using the individual block locks. each 64kb block (except the top and bot tom blocks , total of 510 blocks ) and each 4kb sector within the top/bottom blocks (total of 32 sectors) are equipped with an individual block lock bit. when the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, erase or program commands issued to the corresponding sector or block will be ignored. when the device is powered on, all individual block lock bits will b e 1, so the entire memory array is protected from erase/program. an individual block unl ock (39h) instruction must be issued to unlock any specific sector or block. the wps bit in status register - 3 is used to decide which write protect scheme should be u sed. when wps=0 (factory default), the device will only utilize cmp, sec, tb, bp[2 :0] bits to protect specific areas of the arra y; when wps=1, the device will utilize the individual block locks for write protection.
w25q32fv publication release date: june 03, 2016 - 16 - revision j 7. status and configuration registers thre e status and configuration registers are provided for w 25q32fv . the read status register - 1/ 2 /3 instruction s can be used to provide sta tus on the availability of the flash memory array, whether the device is write enabled or disabled, t he state of write pro tection , quad spi s e tting , se curity register lock status, erase/program suspend status , output driver strength, power - up and current address mode . the write status register instruction can be used to configure the device write protection features , quad sp i sett i ng , security register otp lock s, hold/reset functions, output driver strength and power - up address mode . write access to the status register is controlled by the state of the non - volatile s tatus register protect bits (srp 0, srp1 ) , the write enable instruction, and during standard/dual spi operations, the /wp pin . 7.1 status registers figure 4 a . status register - 1 7.1.1 erase/write in progress ( busy ) C status only busy is a read only bit in the status register (s0) that is set to a 1 state when the device is executing a page program, quad page program, sector erase, block erase, chip erase, write status register or erase/program security register instruction. during this time the device will ignore further instructions except for the read status register a nd erase /program suspend instruction (see t w , t pp , t se , t b e , and t c e in ac characteristics). when the program, erase or write status /security register instruction has completed, the busy bit will be cleared to a 0 state indicating the device is ready for f urther instructions. 7.1.2 write enable latch (wel) C status only write enable latch (wel) is a read only bit in the statu s register (s1) that is set to 1 after executing a write enable instruction. th e wel status bit is cleared to 0 when the device is write di sabled. a write disable state occurs upon power - up or after any of the following instructions: write disable, page program, quad page program, sector erase, block erase, chip erase, write status register , erase security register and program security regist er . 7.1.3 block protect bits (bp2, bp1, bp0) C volatile/non - volatile writable the block protect bits (bp2, bp1, bp0 ) are non - volatile read/write bits in the status register (s4, s3, and s2 ) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (see status register memory protection table). the factory default setting f or the block protection bits is 0, none of the array protected. s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 s r p 0 s e c t b b p 2 b p 1 b p 0 w e l b u s y s t a t u s r e g i s t e r p r o t e c t 0 ( v o l a t i l e / n o n - v o l a t i l e w r i t a b l e ) t o p / b o t t o m p r o t e c t b i t ( v o l a t i l e / n o n - v o l a t i l e w r i t a b l e ) b l o c k p r o t e c t b i t s ( v o l a t i l e / n o n - v o l a t i l e w r i t a b l e ) w r i t e e n a b l e l a t c h ( s t a t u s - o n l y ) e r a s e / w r i t e i n p r o g r e s s ( s t a t u s - o n l y ) s e c t o r p r o t e c t b i t ( v o l a t i l e / n o n - v o l a t i l e w r i t a b l e )
w25q32fv - 17 - 7.1.4 top/bottom block protect (tb) C volatile/non - volatile writable the non - volatile top/bottom bit (tb) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the botto m (tb=1) of the array as shown in the status register memory protection table. the f actory default setting is tb=0. the tb bit can be set with the write status register instruction depending on the state of the srp0, srp1 and wel bits. 7.1.5 sector /block protec t bit (sec) C volatile/non - volatile writable the non - volatile sector /block p rotect bit (sec) controls if the block protect bits (bp2, bp1, bp0) protect either 4kb sectors (sec=1) or 64kb blocks (sec=0) in the top (tb=0) or the bottom (tb=1) of the array a s shown in the status register memory protection table. the default setting is sec =0 . 7.1.6 complement protect (cmp) C volatile/non - volatile writable the c omplement p rotect bit (cmp) is a non - volatile read/write bit in the status register (s14). it is used in co njunction with sec, tb, bp2, bp1 and bp0 bits to provide more flexibility for the array protection. once cmp is set to 1, previo us array protection set by sec, tb, bp2, bp1 and bp0 will be reversed. for instance, when cmp=0, a top 6 4kb block can be protect ed while the rest of the array is not; when cmp=1, the top 6 4kb block will become unprotected while the rest of the array become read - only. please refer to the status register memory protection table for details. the default setting is cmp =0. 7.1.7 status regist er protect (srp 1 , srp 0 ) C volatile/non - volatile writable the status register protect bits (srp 1 and srp0 ) are non - volatile read/write bits in the status register (s8 and s7). the srp bits control the method of write protection: s oftware p rotection, h ardwar e p rotection, p ower s upply l ock - d own or o ne t ime p rogrammable (otp) p rotection. srp1 srp0 /wp status register description 0 0 x software protection /wp pin has no control. the status register can be written to after a write enable instruction , wel=1 . [fac tory default] 0 1 0 hardware protect ed when /wp pin is low the status register locked and can not be written to . 0 1 1 hardware unprotected when /wp pin is high the status register is unlocked and can be written to after a write enable instruction , wel= 1. 1 0 x power supply lock - down status register is protected and can not be written to again until the next power - down , power - up cycle . ( 1 ) 1 1 x one time program ( 2 ) status register is permanently protected and can not be written to. note s : 1. when srp1, srp0 = (1, 0), a power - down, power - up cycle will change srp1, srp0 to (0, 0) state. 2. this feature is available upon special order. please contact winbond for details.
w25q32fv publication release date: june 03, 2016 - 18 - revision j figure 4 b . status register - 2 7.1.8 erase/program suspend status (sus) C status only t he suspend status bit is a read only bit in the status register (s15) that is set to 1 after executing a erase/program suspend (75h) instruction. the sus status bit is cleared to 0 by erase/program resume (7ah) instr uction as well as a power - down, power - up cycle. 7.1.9 security register lock bits (lb3, lb2, lb1 ) C volatile/non - volatile otp writable the security regist er lock bits (lb3, lb2, lb1 ) are non - volatile one time program (otp) bits in sta tus register (s13, s12, s11 ) that provide the write protect control and status to the security registers . t he default state of lb3 - 1 is 0, securi ty registers are unlocked. lb3 - 1 can be set to 1 individually using the write status register instruction. lb3 - 1 are one time programmable (otp), once its set to 1, the correspon ding 256 - byte security register will become read - only permanently. 7.1.10 quad enable ( qe ) C volatile/non - volatile writable the quad enable (qe ) bit is a non - volatile read/write bit in the status register (s 9 ) that allow s quad spi and qpi operation . when the qe b it is set to a 0 state (factory default for part numbers with ordering options ig, and if ) , the /wp pin and /hold are enabled . when the qe bit is set to a 1 (factory default for quad enabled part numbers with ordering option iq), , the quad io2 and i o3 pins are enabled , and /wp and /hold functions are disabled . qe bit is required to be set to a 1 before issuing an enter qpi (38h) to switch the device from standard/dual/quad spi to qpi, otherwise the command will be ignored. when the device is in qpi m ode, qe bit will remain to be 1. a write status register command in qpi mode cannot change qe bit from a 1 to a 0. warning: if the /wp or /hold pins are tied directly to the power supply or ground during standard spi or dual spi operation, the qe bit should never be set to a 1. s 1 5 s 1 4 s 1 3 s 1 2 s 1 1 s 1 0 s 9 s 8 s u s c m p l b 3 l b 2 l b 1 ( r ) q e s r p 1 s t a t u s r e g i s t e r p r o t e c t 1 ( v o l a t i l e / n o n - v o l a t i l e w r i t a b l e ) c o m p l e m e n t p r o t e c t ( v o l a t i l e / n o n - v o l a t i l e w r i t a b l e ) s e c u r i t y r e g i s t e r l o c k b i t s ( v o l a t i l e / n o n - v o l a t i l e o t p w r i t a b l e ) r e s e r v e d q u a d e n a b l e ( v o l a t i l e / n o n - v o l a t i l e w r i t a b l e ) s u s p e n d s t a t u s ( s t a t u s - o n l y )
w25q32fv - 19 - figure 4 c . status register - 3 7.1.11 write protect selection (wp s) C volatile/non - volatile writable the wps bit is used to select which write protect scheme should be used . when wps=0, the device will use the combination o f cmp, s ec, tb, bp[2 :0] bits to protect a specific area of the memory array. when wps=1, the device will utilize the individual block locks to protect any individual sector or blocks. the default value for all individual block lock bits is 1 upon device power on o r after reset. 7.1.12 output driver strength (drv1, drv0) C volatile/non - volatile writable the drv1 & drv0 bits are used to determine the output driver strength for the read operations . drv1, drv0 driver strength 0, 0 100% 0, 1 75% 1, 0 50% 1, 1 25% (default) 7.1.13 /hold or / reset pin function (hold/rst) C volatile/non - volatile writable the hold/rst bit is used to determine whether /hold or /reset function should be implemented on the hardware pin for 8 - pin packages . when hold/rst=0 (factory default), the pin acts as /hold; when hold/rst=1, the pin acts as /reset. however, /hold or /reset functions are only available when qe=0. if qe is set to 1, the /hold and /reset functions are disabled, the pin acts as a dedicated data i/o pin. s 2 3 s 2 2 s 2 1 s 2 0 s 1 9 s 1 8 s 1 7 s 1 6 h o l d / r s t d r v 1 d r v 0 ( r ) ( r ) w p s o u t p u t d r i v e r s t r e n g t h ( v o l a t i l e / n o n - v o l a t i l e w r i t a b l e ) r e s e r v e d w r i t e p r o t e c t s e l e c t i o n ( v o l a t i l e / n o n - v o l a t i l e w r i t a b l e ) / h o l d o r / r e s e t f u n c t i o n ( v o l a t i l e / n o n - v o l a t i l e w r i t a b l e ) ( r ) ( r ) r e s e r v e d
w25q32fv publication release date: june 03, 2016 - 20 - revision j 7.1.14 reserved bits C non functional the re are a few reserved status register bits that may be read out as a 0 or 1. it is recommended to ignore the values of those bits. during a write status register instruction, the reserved bits can be written as 0, but there will not be any effects.
w25q32fv - 21 - 7.1.15 w 25q32fv s tatus register memory protection ( wps = 0 , cmp = 0 ) status register (1) w25q32 f v (32m - bit) memory protecti on (3) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 none none none none 0 0 0 0 1 63 3f0000h C 3fffffh 64kb upper 1/64 0 0 0 1 0 62 and 63 3e0000h C 3fffffh 128kb upper 1/32 0 0 0 1 1 60 thru 63 3c0000h C 3fffffh 256kb upper 1/16 0 0 1 0 0 56 thru 63 380000h C 3fffffh 512kb upper 1/8 0 0 1 0 1 48 thru 63 300000h C 3fffffh 1 mb upper 1/4 0 0 1 1 0 32 thru 63 200000h C 3fffffh 2mb upper 1/2 0 1 0 0 1 0 000000h C 00ffffh 64kb lower 1/64 0 1 0 1 0 0 and 1 000000h C 01ffffh 128kb lower 1/32 0 1 0 1 1 0 thru 3 000000h C 03ffffh 256kb lower 1/16 0 1 1 0 0 0 thru 7 000000h C 07f fffh 512kb lower 1/8 0 1 1 0 1 0 thru 15 000000h C 0fffffh 1mb lower 1/4 0 1 1 1 0 0 thru 31 000000h C 1fffffh 2mb lower 1/2 x x 1 1 1 0 thru 63 000000h C 3f ffffh 4mb all 1 0 0 0 1 63 3ff000 h C 3f ffffh 4kb u - 1/1024 1 0 0 1 0 63 3fe000 h C 3f ffffh 8kb u - 1/512 1 0 0 1 1 63 3fc000 h C 3f ffffh 16kb u - 1/256 1 0 1 0 x 63 3f8000 h C 3f ffffh 32kb u - 1/128 1 1 0 0 1 0 000000h C 000fffh 4kb l - 1/1024 1 1 0 1 0 0 000000h C 001fffh 8kb l - 1/512 1 1 0 1 1 0 000000h C 003fffh 16kb l - 1/256 1 1 1 0 x 0 000000h C 007fffh 32kb l - 1/128 note s : 1. x = dont care 2. l = lower; u = upper 3. i f any erase or program command specifies a memory region that contains protected data portion, this command will be ignored
w25q32fv publication release date: june 03, 2016 - 22 - revision j 7.1.16 w 25q32fv status register memory protection ( wps = 0 , cmp = 1) status register (1) w25q32 f v (32m - bit) memory protecti on (3) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 0 thru 63 000000h C 3fffffh 4mb all 0 0 0 0 1 0 thru 62 000000h C 3effffh 4,032kb lower 63/64 0 0 0 1 0 0 and 61 000000h C 3dffffh 3,968kb lower 31/32 0 0 0 1 1 0 thru 59 000000h C 3bffffh 3,840kb lower 15/16 0 0 1 0 0 0 thru 55 000000h C 37ffffh 3,584kb lower 7/8 0 0 1 0 1 0 thru 47 000000h C 2fffffh 3mb lower 3/4 0 0 1 1 0 0 thru 31 000000h C 1fffffh 2mb lower 1/2 0 1 0 0 1 1 thru 63 010000h C 3fffffh 4,032kb upper 63/64 0 1 0 1 0 2 and 63 020000h C 3fffffh 3,968kb upper 31/32 0 1 0 1 1 4 thru 63 040000h C 3fffffh 3,840kb upper 15/16 0 1 1 0 0 8 thru 63 080000h C 3ffff fh 3,584kb upper 7/8 0 1 1 0 1 16 thru 63 100000h C 3fffffh 3mb upper 3/4 0 1 1 1 0 32 thru 63 200000h C 3fffffh 2mb upper 1/2 x x 1 1 1 none none none none 1 0 0 0 1 0 thru 63 000 000 h C 3f efffh 4,092 kb l - 1023/1024 1 0 0 1 0 0 thru 63 000 000 h C 3f df ffh 4,08 8kb l - 511/512 1 0 0 1 1 0 thru 63 000 000 h C 3f bfffh 4,080 kb l - 255/256 1 0 1 0 x 0 thru 63 000 000 h C 3f 7fffh 4,064 kb l - 127/128 1 1 0 0 1 0 thru 63 00 1 000h C 3ff fffh 4,092 kb u - 1023/1024 1 1 0 1 0 0 thru 63 00 2 000h C 3ff fffh 4,08 8kb u - 5 11/512 1 1 0 1 1 0 thru 63 00 4 000h C 3ff fffh 4,080 kb u - 255/256 1 1 1 0 x 0 thru 63 00 8 000h C 3ff fffh 4,064 kb u - 127/128 notes: 4. x = dont care 5. l = lower; u = upper 6. i f any erase or program command specifies a memory region that contains protected data portion, this command will be ignored
w25q32fv - 23 - 7.1.17 w 25q32fv individual block memory protection (wps=1) figure 4 d . individual block/sector locks note s : 1. individual block/sector protection is only valid when wps=1. 2. all individual block/sector lock bits are set to 1 by default after power up, all memory array is protected. s e c t o r 0 ( 4 k b ) s e c t o r 1 ( 4 k b ) s e c t o r 1 4 ( 4 k b ) s e c t o r 1 5 ( 4 k b ) b l o c k 1 ( 6 4 k b ) b l o c k 6 2 ( 6 4 k b ) s e c t o r 0 ( 4 k b ) s e c t o r 1 ( 4 k b ) s e c t o r 1 4 ( 4 k b ) s e c t o r 1 5 ( 4 k b ) b l o c k 0 ( 6 4 k b ) b l o c k 6 3 ( 6 4 k b ) i n d i v i d u a l b l o c k l o c k s : 3 2 s e c t o r s ( t o p / b o t t o m ) 6 2 b l o c k s i n d i v i d u a l b l o c k l o c k : 3 6 h + a d d r e s s i n d i v i d u a l b l o c k u n l o c k : 3 9 h + a d d r e s s r e a d b l o c k l o c k : 3 d h + a d d r e s s g l o b a l b l o c k l o c k : 7 e h g l o b a l b l o c k u n l o c k : 9 8 h
w25q32fv publication release date: june 03, 2016 - 24 - revision j 8. instructions the standard/dual/quad spi instruction set of the w 25q32fv consists of 4 5 basic instructions that are fully controlled through the spi bus (see instruction set t able 1 - 2 ). instruc tions are initiated with the falling edge of chip select (/cs) . the first byte of data clo cked into the di input provides the i nstruction code. data on the di input is sampled on the rising edge of clock with mo st significant bit (msb) first. the qpi instr uction set of the w 25q32fv consists of 3 2 basic instructions that are fully controlled through the spi bus (see instruction set t able 3 ). instructions are initiated with the falling edge of chip select (/cs). the first byte of data clocked through io[3:0] pins provides the instruction code. data on all four io pins are sampled on the rising edge of clock with most significant bit (msb) first. all qpi instructions, addresses, data and dummy bytes are using all four io pins to transfer every byte of data with every two serial clocks (clk). instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (dont care), and in some cases, a combination. instructions are completed with the rising edge of edge /cs . clock relative timing diagrams for each instruction are included in f igures 5 through 5 7 . all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary ( / cs driven high after a full 8 - bits have been clocked) otherwise the instruction will be ignor ed. this feature further protects the device from inadvertent writes. additionally, while the memory is being programmed or erased, or when the status register is bei ng written, all instructions except for read status register will be ignored until the program or erase cycle has completed. 8.1 device id and instruction set tables 8.1.1 manufacturer and device identification manufacturer id (m f 7 - m f 0) winbond serial flash ef h device id (id7 - id0) (id15 - id0) instruction abh, 90h , 92h, 94h 9fh w 25q32fv (spi mode) 1 5 h 4 01 6 h w 25q32fv (qpi mode) 1 5 h 601 6 h
w25q32fv - 25 - 8.1.2 instruction set table 1 ( standard /dual/quad spi instructions ) (1) data input output byte 1 byte 2 byte 3 byte 4 byt e 5 byte 6 byte 7 clock number (0 C 7) (8 C 15) (16 C 23) (24 C 31) (32 C 39) (40 C 47) (48 C 55) write enable 06h volatile sr write enable 50h write disable 04h read status register - 1 05h (s7 - s0) (2) write status register - 1 (4) 01h (s7 - s0) (4) read status register - 2 35h (s15 - s8) (2) write status register - 2 31h (s15 - s8) read status register - 3 15h (s23 - s16) (2) write status register - 3 11h (s23 - s16) chip erase c7h /60h erase / program suspend 75h erase / program resume 7ah power - down b9h release power - down / id abh dummy dummy dummy (id7 - id0) (2) manufacturer/device id 90h dummy dummy 00h (mf7 - mf0) (id7 - id0) jedec id 9fh (mf7 - mf0) (id15 - id8) (id7 - id0) global block lock 7eh global block unlock 98h enter qpi mode 38h en able reset 66h reset device 99h
w25q32fv publication release date: june 03, 2016 - 26 - revision j 8.1.3 instruction set table 2 (standard/dual/quad spi instructions ) (1) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 clock number (0 C 7) (8 C 15) (16 C 23) (24 C 31) (32 C 39) (40 C 47) read unique id 4bh dummy dummy dummy dummy (uid63 - uid0) page program 02h a23 - a16 a15 - a8 a7 - a0 d7 - d0 d7 - d0 (3) quad page program 3 2h a23 - a16 a15 - a8 a7 - a0 d7 - d0 , (9) d7 - d0 , (3) sector erase (4kb) 20h a23 - a16 a15 - a8 a7 - a0 block erase (32kb) 52h a23 - a16 a15 - a8 a7 - a0 blo ck erase (64kb) d8h a23 - a16 a15 - a8 a7 - a0 read data 03h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) fast read 0bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) fast read dual output 3bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (7) fast read quad output 6bh a23 - a16 a15 - a8 a7 - a0 dum my (d7 - d0 , ) (9) read sfdp register 5ah a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) erase security register (5) 44h a23 - a16 a15 - a8 a7 - a0 program security register (5) 42h a23 - a16 a15 - a8 a7 - a0 d7 - d0 d7 - d0 (3) read security register (5) 48h a23 - a16 a15 - a8 a7 - a0 dumm y (d7 - d0) individual block lock 36h a23 - a16 a15 - a8 a7 - a0 individual block unlock 39h a23 - a16 a15 - a8 a7 - a0 read block lock 3 d h a23 - a16 a15 - a8 a7 - a0 (l 7 - l 0 ) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 clock number (0 C 7) (8 C 11) (12 C 15) (16 C 19) (20 C 23) (24 C 27) (28 C 31) fast read dual i/o bbh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) mftr./device id dual i/o 92h a23 - a16 a15 - a8 a7 - a0 dummy (mf7 - mf0) (id7 - id0) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 byte 8 byte 9 clock number (0 C 7) (8, 9) (10, 11) (12, 13) (14, 15 ) (16, 17) (18, 19) (20, 21) (22, 23) set burst with wrap 77h dummy dummy dummy w8 - w0 fast read quad i/o ebh a23 - a16 a15 - a8 a7 - a0 m7 - m0 dummy dummy (d7 - d0) (d7 - d0) word read quad i/ o (12) e7h a23 - a16 a15 - a8 a7 - a0 m7 - m0 dummy (d7 - d0) (d7 - d0) (d7 - d0) octal word read quad i/o (13) e3h a23 - a16 a15 - a8 a7 - a0 m7 - m0 (d7 - d0) (d7 - d0) (d7 - d0) (d7 - d0) mftr./device id quad i/o 94h a23 - a16 a15 - a8 a7 - a0 m7 - m0 dummy dummy (mf7 - mf0) (id7 - id0)
w25q32fv - 27 - 8.1.4 inst ruction set table 3 (qpi instructions ) (14) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 clock number (0 , 1) (2 , 3) (4, 5) (6 , 7) (8 , 9) (10 , 11) write enable 06h volatile sr write enable 50h write disable 04h read status register - 1 0 5h (s7 - s0) (2) write status register - 1 (4) 01h (s7 - s0) (4) read status register - 2 35h (s15 - s8) (2) write status register - 2 31h (s15 - s8) read status register - 3 15h (s23 - s16) (2) write status register - 3 11h (s23 - s16) chip erase c7h /60h erase / progr am suspend 75h erase / program resume 7ah power - down b9h set read parameters c0h p7 - p0 release powerdown / id abh dummy dummy dummy (id7 - id0) (2) manufacturer/device id 90h dummy dummy 00h (mf7 - mf0) (id7 - id0) jedec id 9fh (mf7 - mf0) (id15 - id8) (id 7 - id0) global block lock 7eh global block unlock 98h exit qpi mode ffh enable reset 66h reset device 99h page program 02h a23 - a16 a15 - a8 a7 - a0 d7 - d0 (9) d7 - d0 (3) sector erase (4kb) 20h a23 - a16 a15 - a8 a7 - a0 block erase (32kb) 52h a23 - a16 a15 - a 8 a7 - a0 block erase (64kb) d8h a23 - a16 a15 - a8 a7 - a0 fast read 0bh a23 - a16 a15 - a8 a7 - a0 dummy (15) (d7 - d0) burst read with wrap (16) 0ch a23 - a16 a15 - a8 a7 - a0 dummy (15) (d7 - d0) fast read quad i/o ebh a23 - a16 a15 - a8 a7 - a0 m7 - m0 (15) (d7 - d0) individual blo ck lock 36h a23 - a16 a15 - a8 a7 - a0 individual block unlock 39h a23 - a16 a15 - a8 a7 - a0 read block lock 3 d h a23 - a16 a15 - a8 a7 - a0 (l7 - l0)
w25q32fv publication release date: june 03, 2016 - 28 - revision j notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ( ) indicate da ta output from the device on either 1, 2 or 4 io pins. 2. the status register contents and device id will repeat continuously until /cs terminates the instruction. 3. at least one byte of data input is required for page program, quad page program and program sec urity registers, up to 256 bytes of data input. if more than 256 bytes of data are sent to the device , the addressing will wrap to the beginning of the page and overwrite previously sent data. 4. write status register - 1 (01h) can also be used to program statu s register - 1&2, see section 8.2.5 . 5. security register address: security register 1: a23 - 16 = 00h; a15 - 8 = 10h; a7 - 0 = byte address security register 2: a23 - 16 = 00h; a15 - 8 = 20h; a7 - 0 = byte address security register 3: a23 - 16 = 00h; a15 - 8 = 30h; a7 - 0 = byte address 6. dual spi address input format: io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 7. dual spi data output format: io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 8. quad spi address input format: set burst with wrap input format: io0 = a20, a16, a12, a8, a4, a0, m4, m0 io0 = x, x, x, x , x, x, w4, x io1 = a21, a17, a13, a9, a5, a1, m5, m1 io1 = x, x, x, x, x, x, w5, x io2 = a22, a18, a14, a10, a6, a2, m6, m2 io2 = x, x, x, x, x, x, w6, x io3 = a23, a19, a15, a11, a7, a3, m7, m3 io 3 = x, x, x, x, x, x, x, x 9. quad spi data input/output format: io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3, ..) 10. fast read quad i / o data output format: io0 = (x, x, x, x, d4, d 0, d4, d0) io1 = (x, x, x, x, d5, d1, d5, d1) io2 = (x, x, x, x, d6, d2, d6, d2) io3 = (x, x, x, x, d7, d3, d7, d3) 11. word read quad i/o data output format: io0 = (x, x, d4, d0, d4, d0, d4, d0) io1 = (x, x, d 5, d1, d5, d1, d5, d1) io2 = (x, x, d6, d2, d6, d2, d6, d2) io3 = (x, x, d7, d3, d7, d3, d7, d3) 12. for word read quad i/o, t he lowest address bit must be 0. (a0 = 0) 13. for octal word read quad i/o, t he lowest four address bits must be 0. (a 3, a2, a1, a0 = 0) 14. qpi command, address, data input/output format: clk # 0 1 2 3 4 5 6 7 8 9 10 11 io0 = c4, c0, a20, a16, a12, a8, a4, a0, d4, d0 , d4, d0 io1 = c5, c1, a21, a17, a13, a9 , a5, a1, d5, d1 , d5, d1 io2 = c6, c2, a22, a18, a14, a10, a6, a2, d6, d2 , d6, d2 io3 = c7, c3, a23, a19, a15, a11, a7, a3, d7, d3 , d7, d3 15. the number of dummy clock s for qpi fast read , qpi fast read quad i/o & qpi burst re ad with wrap is controlled by read parameter p7 C p4. 16. the wrap around length for qpi burst read with wrap is controlled by read parameter p3 C p0.
w25q32fv - 29 - 8.2 instruction descriptions 8.2.1 write enable (06 h) the write en able instruction (figure 5 ) sets the write enable la tch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, quad page program, sector erase, block erase , chip erase, write status register and erase/program security registers instruction. the write enable instruction is entered by driving /cs low, shifting the instruction code 06h into the data input (di) pin on the rising edge of clk, and then driving /cs high. figure 5 . write en able instruction for spi mode (left ) or qpi mode (right) 8.2.2 write enable for volatil e status register (50h) the non - volatile status register bits described in section 7 .1 can also be written to as volatile bits. this gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typ ical non - volatile bit write cycles or affecting the endurance of the status register non - volatile bits. to write the volatile values into the status register bits, the write enable for volatile status register (50h) instruction must be issued prior to a wr ite status register (01h) instruction. write enable for volatile status register instruction (figure 6 ) will not set the write enable latch (wel) bit, it is only valid for the write status register instruction to change the volatile status register bit val ues. figure 6 . write enable for volat ile status register instruction for spi mode (left) or qpi mode (right ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (06h) high impedance /cs clk mode 0 mode 3 0 1 mode 0 mode 3 io 0 io 1 io 2 io 3 06h instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (50h) high impedance /cs clk mode 0 mode 3 0 1 mode 0 mode 3 io 0 io 1 io 2 io 3 50h instruction
w25q32fv publication release date: june 03, 2016 - 30 - revision j 8.2.3 write disable (04 h) the write dis able instruction (figure 7 ) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving /cs low, shifting the instructio n code 04h into the di pin and then driving /cs high. note that the wel bit is automatically reset after power - up and upon completion of the write status register, erase/program se curity registers, page program, quad page program, sector erase, block erase, chip erase and reset instructions. figure 7 . write dis able instruction for spi mode (left ) or qpi mode (right) 8.2.4 read status register - 1 (05h), status register - 2 ( 3 5h) & status register - 3 (15h) the read status register instruction s allow the 8 - bit status register s to be read. the instruction is entered by driving /cs low and shifting the instruction code 05h for status register - 1, 35h for status r egister - 2 or 15h for statu s register - 3 into the di pin on the rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in f igure 8 . refer to section 7.1 for status register descriptions . the read status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept a nother instruction. the status register can be read continuously, as shown in figure 8 . the instruction is completed by driving /cs high. figure 8 a . read status register instruction (spi mode ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (04h) high impedance /cs clk mode 0 mode 3 0 1 mode 0 mode 3 io 0 io 1 io 2 io 3 04h instruction / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 0 5 h / 3 5 h / 1 5 h ) h i g h i m p e d a n c e 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 s t a t u s r e g i s t e r - 1 / 2 / 3 o u t s t a t u s r e g i s t e r - 1 / 2 / 3 o u t * * = m s b *
w25q32fv - 31 - figure 8 b. read status register instruction (qpi mode ) 8.2.5 write status register - 1 (01h), status register - 2 ( 3 1h) & status register - 3 (11h) the write status register instruction allows the status register s to be written. the writable status register bi ts include: srp0, sec, tb, bp[2 :0] in status register - 1; cmp, lb[3:1], qe, s r p 1 in status register - 2; hol d/rst, drv1, drv0, wps & adp in status register - 3 . all other status register bit locations are read - only and will not be affected by the write status register instruction. lb [3:1] are non - volatile otp bi ts, once i t is set to 1, it can not be cleared to 0. to write non - volatile status register bits, a standard write enable (06h) instruction must previously have been executed for the device to accept the write status register i nstruction (status register bit wel must equal 1). once write enabled, the instruction is entered by driving /cs low, sending the instruction code 01h /31h/11h , and then writing the status register data byte as illustrated in figure 9 a & 9b . to write volatile status register bits, a write enabl e for volatile status register (50h) instruction must have been executed prior to the write status register instruction (status register bit wel remains 0). however, srp1 and lb[3:1] cannot be changed from 1 to 0 because of the otp protection for these bits. upon power off or the execution of a software/hardware reset , the volatile status register bit values will be lost, and the non - volatile status register bit values will be restored . during non - volatile status register write operation (06h combined w ith 01h / 31h/ 11h ), after /cs is driven high, the self - timed write status register cycle will commence for a time duration of t w (see ac characteristics). while the write status register cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept other instructions again. after the write status register cycle has finished, the write enable latch (wel) bit in the status register will be cleared to 0. / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 0 5 h / 3 5 h / 1 5 h 2 3 4 5 4 0 4 0 5 1 6 2 7 3 5 1 6 2 7 3 4 5 6 7 s r - 1 / 2 / 3 o u t s r - 1 / 2 / 3 o u t i n s t r u c t i o n
w25q32fv publication release date: june 03, 2016 - 32 - revision j during volatile status register write operation (50h combined with 01h / 31h/ 11h ), after /cs is driven high, the status register bits will be refreshed to the new values within the time period of t shsl2 (see ac characteristics). busy bit will remain 0 during the status register bit refresh period. the write status register instruction can be used in both spi mode and qpi mode. however, the qe bit cannot be written to when the device is in the qpi mo de, because qe=1 is required for the device to enter and operate in the qpi mode. refer to section 7.1 fo r status register descriptions. figure 9a. write status register - 1/2/3 instruction (spi mode) figure 9b. write status register - 1/2/ 3 instruction (qpi mode) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 0 1 h / 3 1 h / 1 1 h ) h i g h i m p e d a n c e 8 9 1 0 1 1 1 2 1 3 1 4 1 5 7 6 5 4 3 2 1 0 r e g i s t e r - 1 / 2 / 3 i n m o d e 0 m o d e 3 * = m s b * / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 0 1 / 3 1 / 1 1 h 2 3 4 0 5 1 6 2 7 3 s r 1 / 2 / 3 i n m o d e 0 m o d e 3 i n s t r u c t i o n
w25q32fv - 33 - the w 25q32fv is also backward compatible to winbonds previous generations of serial flash memories, in which the status register - 1&2 can be written using a single write status register - 1 (01h) command. to complete the write status register - 1 & 2 instruction, the /cs pin must be driven high after the sixteenth bit of data that is clocked in as shown in figure 9c & 9d . if /cs is driven high after the eighth clock, the write status register - 1 (01h) instruction will only program the status register - 1, the status register - 2 will not be affected (previous generations will clear cmp and qe bits) . figure 9 c . write status register - 1/2 instruction (spi mode ) figure 9 d . write status register - 1/2 instruction (qpi mode ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (01h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 status register 1 in status register 2 in mode 0 mode 3 * * = msb * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 01h 2 3 4 5 4 0 12 8 5 1 6 2 7 3 13 9 14 10 15 11 sr1 in sr2 in mode 0 mode 3 instruction
w25q32fv publication release date: june 03, 2016 - 34 - revision j 8.2.6 read data (03h) the read data instruction allows one or more data bytes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin low and the n shif ting the instruction code 03h followed by a 24 - b it address (a23 - a0) into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shif ted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving /cs high. the read data instruction sequence is shown in figure 1 4 . if a read data instruction is issued while an erase, progra m or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). the read data (03h) instru ction is only supported in standard spi mode. figure 1 4 . read data instruction (spi mode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (03h) high impedance 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 7 6 5 4 3 2 1 0 7 24-bit address 23 22 21 3 2 1 0 data out 1 * * = msb *
w25q32fv - 35 - 8.2.7 fast read (0bh) the fast read instruction is similar to the read data instruction except that it can operate at the highest possib le frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 1 6 . the dummy clocks allow the devices internal circuits additional time for setting up the initial addr ess. during the dummy clocks the data value on the d o pin is a dont care. figure 1 6 a . fast read instruction (spi mode ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (0bh) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy clocks high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 43 31 0 = msb *
w25q32fv publication release date: june 03, 2016 - 36 - revision j fast read (0bh) in qpi mode the fast read instruction is also supported in qpi mode. when qpi mode is enabled, the number of d ummy clocks is configured by the set read parameters (c0h) instruction to accommodate a wide range of applications with different needs for either maximum fast read frequency or minimum data access latency. depending on the read parameter bits p[5:4] set ting , the number of dummy clocks can be configured as either 2, 4, 6 or 8. the default number of dummy clocks upon power up or after a reset instruction is 2 . figure 1 6 b . fast read instruction (qpi mode ) /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 0bh 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 dummy * byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 4 5 6 7 ios switch from input to output * "set read parameters" instruction (c0h) can set the number of dummy clocks. instruction
w25q32fv - 37 - 8.2.8 fast read dual output (3bh) the fast read dual output (3bh) instruction is similar to the standard fast read (0bh) instruction except th at data is output on two pins ; i o 0 and io 1 . this allows data to be transferred at twice the rate of standard spi devices. the fast read dual output instruction is ide al for quickly downloading code from flash to ram upon power - up or for applications that cache code - segments to ram for execution. similar to the fast read instruction, the fast read dual output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in f igure 1 8 . the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input data during the dummy clocks is dont care. however, the io 0 pin should be high - impedance prior to the falling edge of the first data out clock. figure 1 8 . fast read dual output instruction (spi mode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (3bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 6 4 2 0 24-bit address 23 22 21 3 2 1 0 * * 31 31 /cs clk di (io 0 ) do (io 1 ) dummy clocks 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 7 5 3 1 high impedance 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 io 0 switches from input to output 6 7 data out 1 * data out 2 * data out 3 * data out 4 = msb *
w25q32fv publication release date: june 03, 2016 - 38 - revision j 8.2.9 fast read quad o utput (6bh) the fast read quad output (6bh) instruction is similar to the fast read dual output (3bh) instruction except that data is output on four pins, io 0 , io 1 , io 2 , and io 3 . the quad e nable (qe) bit in status register - 2 must be set to 1 before the de vice will accept the fast read quad output instruction . the fast read quad output instruction allows data to be transferred at four times the rate of stan dard spi devices. t he fast read q ua d output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in f igure 20 . the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the in put data during the dummy clocks is dont care. however, the io pins should be high - impedance prior to the falling edge of the first data out clock. figure 20 . fast read quad output instruction (spi mode only) /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (6bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk dummy clocks 0 40 41 42 43 44 45 46 47 5 1 high impedance 4 5 byte 1 high impedance high impedance 6 2 7 3 high impedance 6 7 high impedance 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 4 io 0 switches from input to output io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 = msb *
w25q32fv - 39 - 8.2.10 f ast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23 - 0) two bits per clock. this reduce d instruction overhead may allow for code execution (xip) directly from the d ua l spi in some applications. fast read dual i/o with continuous read mode the fast read dual i/o instruction can further reduce instruction overhead through setting the co nti nuous read mode b its (m7 - 0) after the input address bits (a23 - 0), as shown in f igure 22 a . the upper nibble of the (m7 - 4) controls the length of the next fast read dual i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read dual i/o instruction (a fter /cs is raised and then lowered) does not require the bbh instruction code, as shown in f igure 22 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuou s read mode bits m5 - 4 do not equal to (1,0), the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. i t is recommended to input ffffh on io0 for the next instruction (16 clo cks), to ensure m4 = 1 and return the device to normal operation. figure 22 a . fast read dual i/ o instruction (initial instruction or previous m5 - 4 ? 10 , spi mode only ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (bbh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 23 /cs clk di (io 0 ) do (io 1 ) 0 32 33 34 35 36 37 38 39 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 22 19 23 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 = msb * *
w25q32fv publication release date: june 03, 2016 - 40 - revision j figure 22 b . fast read dual i/ o instruction (previous instruction set m5 - 4 = 10 , spi mode only ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 15 /cs clk di (io 0 ) do (io 1 ) 0 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 0 1 2 3 4 5 6 7 16 17 18 20 21 22 19 23 * = msb *
w25q32fv - 41 - 8.2.11 fast read quad i/o (ebh) the fast read quad i/o (ebh) instruction is similar to the fast read dual i/o (bbh) instruction except that address and data bits are input and output through four pins io 0 , io 1 , io 2 and io 3 and four dummy clock s are required in spi mode prior to the data output . the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad enable bit (qe) of status register - 2 must be set t o enable the fast r ead quad i/o instruction . fast read quad i/o with continuous read mode the fast read quad i/o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in f igure 24 a . the upper nibble of the (m7 - 4) controls the length of the next fast read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). howe ver, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction (after /cs is raised and then lowered) does not require the ebh instruction code, as shown in f igure 24 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruc tion (after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. it is recommended to input ffh on io0 for the next instruction (8 clocks), to ensure m4 = 1 and return the device to normal operation. figure 24 a . fast read quad i/ o instruction (initial instruction or previous m5 - 4 ? 10 , spi mode ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 22 23 dummy dummy instruction (ebh)
w25q32fv publication release date: june 03, 2016 - 42 - revision j figure 24 b . fast read quad i/ o instructio n ( previous instruction set m5 - 4 = 10 , spi mode ) fast read quad i/o with 8/16/32/64 - byte wrap around in standard spi mode the fast read quad i/o instruction can also be used to access a specific portion within a page by issuing a set burst with wrap (77h) command prior to ebh. the set burst with wrap (77h) command can either enable or disable the wrap around feature for the following ebh commands. when wrap around is enabled, the data being accessed can be limited to either a n 8, 16, 32 or 64 - b yte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 - byte) of data without issuing multiple read comm ands. the set burst with wrap instruction allows three wrap bits, w6 - 4 to be set. the w4 bit is used to enable or disable the wrap around operation while w 6 - 5 are used to specify the length of the wrap around section within a page. refer to section 8.2. 24 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 dummy dummy
w25q32fv - 43 - fast read quad i/o (ebh) in qpi mode the fast read quad i/o instruction is also supported in qpi mode , as shown in figure 1 9 c . when qpi mode is enabled, the number of dummy clocks is configured by the set read parameters (c0h) instruction to accommodate a wide range of applications with different needs for either maximum fast read frequency or minimum data access latency. depending on the read parameter bits p[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. the default number of dummy clocks upon power up or after a reset instruction is 2 . in qpi mode, the continuous read mode bits m7 - 0 are also considered as dummy clocks. in the default setting, the data output will follow the continuo us read mode bits immediately. continuous read mode feature is also available in qpi mode for fast read quad i/o instruction. please refer to the description on previous page s . wrap around feature is not available in qpi mode for fast read quad i/o ins truction. to perform a read operation with fixed data length wrap around in qpi mode, a dedicated burst read with wrap (0ch) instruction must be used. please refer to 8 .2. 45 for details. figure 24 c . fast read quad i/ o instruction (initial instruction or previous m5 - 4 ? 10, qpi mode ) m7-0 * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 ebh 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output * "set read parameters" instruction (c0h) can set the number of dummy clocks. byte 3 instruction
w25q32fv publication release date: june 03, 2016 - 44 - revision j 8.2.12 word read quad i/o (e7h) the word read quad i/o (e 7 h) instruction is similar to the fast read quad i/o ( e bh) instruction except that the lowest a ddress bit (a0) must equ al 0 and only two dummy clock s are required prior to the data output . the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad enable bit (qe) of status register - 2 mu st be set to enable the word r ead quad i/o instruction . word read quad i/o with continuous read mode the word read quad i/o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input addres s bits (a23 - 0), as shown in f igure 2 6 a . the upper nibble of the (m7 - 4) controls the length of the next fast read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction (after /cs is raised and then lowered) does not requi re the e7h instruction code, as shown in f igure 2 6 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the n ext instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. it is recommended to input ffh on io0 for the next instruction (8 clocks), to ensure m4 = 1 and return the device to normal operation. figure 2 6 a . word read quad i/ o instruction (initial instruction or previous m5 - 4 ? 10 , spi mode only ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 dummy instruction (e7h)
w25q32fv - 45 - figure 2 6 b . word read quad i/ o instruction ( previous instruction set m5 - 4 = 10 , spi mode only ) word read quad i/o with 8/16/32/64 - byte wrap around in standard spi mode the word read quad i/o instruction can also be used to access a specific portion within a page by issuing a set burst with wrap (77h) command prior to e7h. the set burst with wrap (77h) command can either enable or disable the wrap around feature for the following e7h commands. when wrap around is enabled, the data being accessed can be limited to eit her a n 8, 16, 32 or 64 - byte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning boundary au tomatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 - byte) of data without is suing multiple read commands. the set burst with wrap instruction allows three wrap bits, w6 - 4 to be set. the w4 bit is used to enable or disable the wrap around operation while w 6 - 5 are used to specify the length of the wrap around section within a page. see 8 .2. 24 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 4 0 5 1 6 2 7 3 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 ios switch from input to output byte 3 8 9 10 11 12 13 dummy
w25q32fv publication release date: june 03, 2016 - 46 - revision j 8.2.13 octal word read quad i/o (e3h) the octal word read quad i/o (e3h) instruction is similar to the fast read quad i/o (ebh) instruction except that the lower four address bits (a0, a1 , a2, a3 ) must equal 0. as a res ult, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (xip). the quad enable bit (qe) of status register - 2 must be se t to enable the octal word r ead quad i/o instruction . octal word read quad i/o with continuous read mode the octal word read quad i/o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in f igure 2 7 a. t he upper nibble of the (m7 - 4) controls the length of the next octal word read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction (after /cs is raised and then lowered) does not require the e3h instruction code, as show n in f igure 2 7 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. it is recommended to input ffh on io0 for the next instruction (8 clocks), to ensure m4 = 1 and return the device to normal operation. figure 2 7 a. octal wo rd read quad i/o instruction ( initial instruction or previous m5 - 4 ? 10 , spi mode only ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 instruction (e3h) 4 0 5 1 6 2 7 3 byte 4
w25q32fv - 47 - figure 2 7 b. octal word read quad i/o instruction ( previous instruction set m5 - 4 = 10 , spi mode only ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 4 0 5 1 6 2 7 3 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 ios switch from input to output byte 3 8 9 10 11 12 13 4 0 5 1 6 2 7 3 byte 4
w25q32fv publication release date: june 03, 2016 - 48 - revision j 8.2.14 set burst with wrap (77h) in standard spi mode, t he set burst with wrap (77h) instruction is used in conjunction with fast read quad i/o and word read quad i/o instructions to access a fixed length of 8/16/32/64 - byte section within a 256 - byte page. certain applications can benefit from this feature and improve the overall system code execution performance. similar to a quad i/o instruction, the set burst with wrap instruction is initiated by driving the /cs pin low and then shifting the instruction code 77h followed by 24 dummy bits and 8 wrap bits, w7 - 0. the instruction sequence is shown in f igure 2 8 . wrap bit w7 and the lower nibble w3 - 0 are not used. w6, w5 w4 = 0 w4 =1 (default) wrap around wrap length wrap around wrap length 0 0 yes 8 - byte no n/a 0 1 yes 16 - byte no n/a 1 0 yes 32 - byte no n/a 1 1 yes 64 - byte no n/a once w6 - 4 is set by a set burst with wrap instruction, all the following fast read quad i/o and word read quad i/o instructions will use the w6 - 4 setting to access the 8/16/32/64 - byte section within any page. to exit the wrap around function and return to normal read operation, another set burst with wrap instruction should be issued to set w4 = 1. the default value of w4 upon power on or after a software/hardware reset is 1. in qpi mode, the burst read with wrap (0ch) instruction should be used to perform the read operation with wrap around feature. the wrap length set by w5 - 4 in standard spi mode is still valid in qpi mode and can also be re - configured by set read parameters (c0h) instruction. refer to 8 .2. 44 and 8 .2. 45 for details. figure 2 8 . set burst with wrap instruction (spi m ode only ) wrap bit /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 x x x x x x x x don't care 6 7 8 9 don't care don't care 10 11 12 13 14 15 instruction (77h) mode 0 mode 3 x x x x x x x x x x x x x x x x w4 x w5 x w6 x x x
w25q32fv - 49 - 8.2.15 pa ge program (02h) the page program instruction allows from one byte to 256 bytes ( a page) of data to be programmed at previously erased (ffh) memory locations. a write en able instruction must be executed before the device will accept the page program instruction (status register bit wel = 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 02h followed by a 24 - bit address (a23 - a0 ) and at l east one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in f igure 2 9 . if an entire 256 byte page is to be pr ogrammed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed s the remaining page length, the addressing will wrap to the beginning of the page. in some case s, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after /cs is driven high, the self - timed page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read statu s register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the page pr ogram cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the page program instruction will not be executed if the addressed page is protected by the block protect ( cmp, sec, tb , bp2, bp1, and bp0 ) bits or the indivi dual block /sector locks . figure 2 9 a . page program instruction (spi mode ) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (02h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q32fv publication release date: june 03, 2016 - 50 - revision j figure 2 9 b . page program instruction (qpi mode ) /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 02h instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte1 byte 2 byte 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 byte 255 byte 256 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 mode 0 mode 3 516 517 518 519
w25q32fv - 51 - 8.2.16 quad input page program ( 3 2h) the quad page program instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io 0 , io 1 , io 2 , and io 3 . the quad page program can improve performance for prom programmer and applications that have slow clock speeds <5mhz. systems wit h faster clock speed will not realize much benefit for the quad page program instruction since the inherent page program time is much greater than the time it take to clock - in the data. to use quad page program the quad enable (qe) bit in stat us register - 2 must be set to 1 . a write enable instruction must be executed before the device will accept the quad page program instruction (status register - 1, wel=1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 32h foll owed by a 24 - bit address (a23 - a0) and at least one data byte, into the io pins. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. all other functions of quad page program are identical to s tandard page program. the quad page program instruction sequence is shown in f igure 30 . figure 30 . quad input page program instruction (spi mode only) /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (32h) 8 9 10 28 29 30 32 33 34 35 36 37 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk 5 1 byte 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 256 0 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 536 537 538 539 540 541 542 543 mode 0 mode 3 byte 253 byte 254 byte 255 io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 * * * * * * * = msb *
w25q32fv publication release date: june 03, 2016 - 52 - revision j 8.2.17 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k - bytes) to t he erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruc tion code 20h followed a 24 - bit sector address (a23 - a0) . the sector erase instructi on sequence is shown in f igure 31 a & 31 b . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase inst ruction will not be executed. after /cs is driven high, the self - timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register instruction may still b e accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be executed if the addressed page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits or the individual block /sector locks . figure 31 a . sector erase instruction (spi mode ) figure 31 b . sector erase instruction (qpi mode ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (20h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 20h instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 mode 0 mode 3
w25q32fv - 53 - 8.2.18 32kb block erase (52h) the block erase instruction sets all memory within a specified block ( 32 k - bytes) to the erased state of all 1s (ffh). a write enable ins truction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 52 h followed a 24 - bit block address (a23 - a0). the block erase instructio n sequence is shown in f igure 32 a & 32 b . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self - timed block erase instruction will commence for a time duration of t be 1 (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect ( cmp , sec, tb, bp2, bp1, and bp0) bits or the individual block/sector locks . figure 32 a . 32kb block erase instruction (spi mode ) figure 32 b . 32kb block erase instruction (qpi mode ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (52h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 52h instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 mode 0 mode 3
w25q32fv publication release date: june 03, 2016 - 54 - revision j 8.2.19 64kb block erase (d8h) the block erase instruction sets all memory within a specified block (64k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will ac cept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code d8h followed a 24 - bit block address (a23 - a0). the block erase instructio n sequence is shown in f igure 33 a & 33 b . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self - timed block erase instruction will commen ce for a time duration of t be (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and bec omes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be execut ed if the addressed page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits or the individual block/sector locks. figure 33 a . 64kb block erase instruction (spi mode ) figure 33 b . 64kb block erase instruction (qpi mode ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (d8h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 d8h instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 mode 0 mode 3
w25q32fv - 55 - 8.2.20 chip erase (c7h / 60h ) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code c7h or 60h . the chip erase instructio n sequence is shown in f igure 34 . the /cs pin must be driven high after t he eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driven high, the self - timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cyc le is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. aft er the chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any memory region is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits or t he individual block/sector locks . figure 34 . chip erase instruction for spi mode (left) or qpi mode (right ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (c7h/60h) high impedance mode 0 mode 3 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 c7h/60h instruction mode 0 mode 3
w25q32fv publication release date: june 03, 2016 - 56 - revision j 8.2.21 erase / program s uspend (75h) the erase/program suspend instruction 75h, allows the system to interrupt a sector or block erase operation or a page program operation and then read from or program/erase data to, any other sectors or blocks. the erase/program suspend instruction sequence is shown in f igure 35 a & 35 b . the write status register instruction (01h) and eras e instructions (20h, 52h, d8h, c7h, 60h, 44h) are not allowed during erase suspend. erase suspend is valid only during the sector or block erase operation. if written during the chip erase operation, the erase suspend instruction is ignored. the write stat us register instruction (01h) and program instructions (02h, 32h, 42h) are not allowed during program suspend. program suspend is valid only during the page program or quad page program operation. the erase/program suspend instruction 75h will be accepte d by the device only if the sus bit in the status register equals to 0 and the busy bit equals to 1 while a sector or block erase or a page program operation is on - going. if the sus bit equals to 1 or the busy bit equals to 0, the suspend instruction will be ignored by the device. a maximum of time of t sus (see ac characteristics) is required to suspend the erase or program operation. the busy bit in the status register will be cleared from 1 to 0 within t sus and the sus bit in the status register will be set from 0 to 1 immediately after erase/program suspend. for a previously resumed erase/program operation, it is also required that the suspend instruction 75h is not issued earlier than a minimum of time of t sus following the preceding resume instr uction 7ah. unexpected power off during the erase/program suspend state will reset the device and release the suspend state. sus bit in the status register will also reset to 0. the data within the page, sector or block that was being suspended may becom e corrupted. it is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. figure 35 a . erase/program suspend instruction (spi mode ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (75h) high impedance mode 0 mode 3 tsus accept instructions
w25q32fv - 57 - fig ure 35 b . erase/program suspend instruction (qpi mode ) /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 75h instruction mode 0 mode 3 tsus accept instructions
w25q32fv publication release date: june 03, 2016 - 58 - revision j 8.2.22 erase / program resume (7ah) the erase/program resume instruction 7ah must be written to resume the sector or block erase operation or the page program operation after an erase/program suspend. the resume instruction 7ah will be accepted by the device only if the sus bit in the status register equals to 1 and the busy bit equals to 0. after issued the sus bit will be cleared from 1 to 0 immediately, the busy bit will be set from 0 to 1 within 200ns and the sector or block will complete the erase operation or the page will complete the program operation. if the sus bit equals to 0 or the busy bit equals to 1, the resume instruction 7ah will be ignored by the device. the erase/program resume instruc tion sequence is shown in f igure 3 6 a & 3 6 b . resume instruction is ignored if the previous erase/program suspend operation was interrupted by unexpected power off. it is also required that a subsequent erase/program suspend instruction not to be issued with in a minimum of time of t sus following a previous resume instruction. figure 3 6 a . erase /program resume instruction (spi mode ) figure 3 6 b . erase/program resume instruction (qpi mode ) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (7ah) mode 0 mode 3 resume previously suspended program or erase /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 7ah instruction mode 0 mode 3 resume previously suspended program or erase
w25q32fv - 59 - 8.2.23 power - down (b9h) although the standby current during normal oper ation is relatively low, standby current can be further reduced with the power - down instruction. the lower power consumption makes the power - down instruction especially useful for battery powered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code b9h as shown in f igure 3 7 a & 3 7 b . the /cs pin must be driven high after the eighth bit has been latched. if this is not done the power - down instruction will not be exe cuted. after /cs is driven high, the power - down state will entered within the time duration of t dp (see ac characteristics). while in the power - down state only the release power - down / device id (abh) instruction, which restores the device to normal operat ion, will be recognized. all other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. the device always powers - up in the normal operation with the standby current of icc1. figure 3 7 a . deep power - down instruction (spi mode ) figure 3 7 b . deep power - down instr uction (qpi mode ) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (b9h) mode 0 mode 3 tdp power-down current stand-by current /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 b9h instruction mode 0 mode 3 tdp power-down current stand-by current
w25q32fv publication release date: june 03, 2016 - 60 - revision j 8.2.24 release power - down / device id (abh) the release from power - down / device id instruction is a multi - purpose instruction. it can be used to release the device from the power - down state , or obtain the devices electronic identification (i d) number. to release the device from the power - down state, the instruction is issued by driving the /cs pin low, shifting the instruction code abh and driving /cs high as shown in f igure 3 8 a & 3 8 b . release from power - down will take the time duration of t res 1 (see ac characteristics) before the device will resume normal operation and other instructions are accepted. the /cs pin must remain high during the t res 1 time duration. when used only to obtain the device id while not in the power - down state, the i nstruction is initiated by driving the /cs pin low and shifting the instruction code abh followed by 3 - dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first . the device id value for the w 25q 32fv is listed in manufacturer and device identification table. the device id can be read continuously. the instruction is completed by driving /cs high. when used to release the device from the power - down state and obtain the device id, the instruction i s the same as previously described, and shown in f igure 3 8 c & 3 8 d , except that after /cs is driven high it must remain high for a time duration of t res 2 (see ac characteristics). after this time duration the device will resume normal operation and other in structions will be accepted. if the release from power - down / device id instruction is issued while an erase, program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle. figure 3 8 a . release power - down instruction (spi mode) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) mode 0 mode 3 tres1 power-down current stand-by current
w25q32fv - 61 - figure 3 8 b . release power - down instruction (qpi mode ) figure 3 8 c . release power - down / device id instruction (spi mode) figure 3 8 d . release power - down / device id instru ction (qpi mode ) /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 abh instruction mode 0 mode 3 tres1 power-down current stand-by current tres2 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) high impedance 8 9 29 30 31 3 dummy bytes 23 22 2 1 0 * mode 0 mode 3 7 6 5 4 3 2 1 0 * 32 33 34 35 36 37 38 device id power-down current stand-by current = msb * power-down current stand-by current device id /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 abh 2 3 4 5 x x x x x x x x 6 7 8 4 0 5 1 6 2 7 3 ios switch from input to output instruction tres2 mode 0 mode 3 x x x x x x x x x x x x x x x x 3 dummy bytes
w25q32fv publication release date: june 03, 2016 - 62 - revision j 8.2.25 read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power - down / device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power - down / device id instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 90h followed by a 24 - bit address (a23 - a0) of 00 0000h. after which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of clk with most significant bit ( msb) first as shown in f igure 3 9 . the device id value s fo r the w 25q32fv are listed in manufacturer and device identification table. the instruction is completed by driving /cs high. figure 3 9 . read m anufacturer / device id instruction (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (90h) high impedance 8 9 10 28 29 30 31 address (000000h) 23 22 21 3 2 1 0 device id * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 manufacturer id (efh) 40 41 42 44 45 46 7 6 5 4 3 2 1 0 * 43 31 0 mode 0 mode 3 = msb *
w25q32fv - 63 - 8.2.26 read manufacturer / device id dual i/o (92h) the read manufacturer / device id dual i/o instruction is an alternative to the read manufacturer / device id instruction that provides both the jedec assigned manufacturer id and the specific device id at 2x speed. the read manufactur er / device id dual i/o instruction is similar to the fast read dual i/o instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 9 2 h followed by a 24 - bit address (a23 - a0) of 000000h , but with the capability to input the address bits two bits per clock . after which, the manufacturer id for winbond (efh) and the device id are shifted out 2 bits per clock on the falling edge of clk with most significant bit s (msb) first as shown in f igure 40 . the device id values for the w 25q32fv are listed in manufacturer and device identi fication table.the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 40 . read manufacturer / device id dual i/o instruction (spi mode only) note: the conti nuous read mode bits m(7 - 0) must be set to fxh to be compatible with fast read dual i/o instruction. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (92h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 5 3 1 * * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 23 * * a23-16 a15-8 a7-0 (00h) m7-0 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 0 mode 0 mode 3 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 6 4 2 1 0 1 mfr id device id mfr id (repeat) device id (repeat) ios switch from input to output * * * * = msb *
w25q32fv publication release date: june 03, 2016 - 64 - revision j 8.2.27 read manufacturer / device id quad i/o (94h) the read manufacturer / device id quad i/o instruction is an alternative to the read manufacturer / device i d instruction that provides both the jedec assigned manufacturer id and the specific device id at 4x speed . the read manufacturer / device id quad i/o instruction is similar to the fast read quad i/o instruction. the instruction is initiated by driving th e /cs pin low and shifting the instruction code 9 4 h followed by a four clock dummy cycles and then a 24 - bit address (a23 - a0) of 000000h , but with the capability to input the address bits four bits per clock . after which, the manufacturer id for winbond ( efh) and the device id are shifted out four bits per clock on the falling edge of clk with most significant bit (msb) first as shown in f igure 41 . the device id values for the w 25q32fv are listed in manufacturer and device identification table. the manufac turer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 41 . read manufacturer / device id quad i/o instruction (spi mode only) note : the continuous read mode bits m(7 - 0) must be set to fxh to be compatible with fast read quad i/o instruction. mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (94h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 5 1 4 0 23 mode 0 mode 3 ios switch from input to output high impedance 7 3 6 2 /cs clk io 0 io 1 io 2 io 3 high impedance a23-16 a15-8 a7-0 (00h) m7-0 mfr id device id dummy dummy /cs clk io 0 io 1 io 2 io 3 23 0 1 2 3 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 24 25 26 27 28 29 30 mfr id (repeat) device id (repeat) mfr id (repeat) device id (repeat)
w25q32fv - 65 - 8.2.28 read unique id number (4bh) the read unique id number instruction accesses a factory - set read - only 64 - bit number that is unique to each w 25q32fv device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the read unique id instruction is initiated by driving the /cs pin low and shifting the instruction code 4bh followed by a four bytes of dummy clocks. after which, the 64 - bit id is shifted out on the falling edge of clk as shown in f igure 42 . figure 42 . read unique id number instruction (spi mode only ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (4bh) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 mode 0 mode 3 * dummy byte 1 dummy byte 2 39 40 41 42 dummy byte 3 dummy byte 4 63 62 61 2 1 0 64-bit unique serial number 100 101 102 high impedance = msb *
w25q32fv publication release date: june 03, 2016 - 66 - revision j 8.2.29 read jedec id (9fh) for compatibility reasons, the w 25q32fv provides several instructions to electronically determine the identity of the device. the read jedec id instruction is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003. the instruction is initiated by driving the /cs pin low and shifting the instruction cod e 9fh. the jedec assigned manufacturer id byte for winbond (efh) and two device id bytes, memory type (id15 - id8) and capacity (id7 - id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in f igure 43 a & 43 b . fo r memory type and capacity values refer to manufacturer and device identification table. figure 43 a . read jedec id instruction (spi mode) figure 43 b . read jedec id instruction (qpi mode ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (9fh) high impedance 8 9 10 12 13 14 15 capacity id7-0 /cs clk di (io 0 ) do (io 1 ) 16 17 18 19 20 21 22 23 manufacturer id (efh) 24 25 26 28 29 30 7 6 5 4 3 2 1 0 * 27 15 mode 0 mode 3 11 7 6 5 4 3 2 1 0 * memory type id15-8 = msb * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 9fh 2 3 4 5 12 8 13 9 14 10 15 11 efh 6 4 0 5 1 6 2 7 3 id15-8 id7-0 ios switch from input to output instruction mode 0 mode 3
w25q32fv - 67 - 8.2.30 read sfdp register (5ah) the w 25q32fv features a 256 - byte serial flash discoverable parameter (sfdp) register that contains information about device configurations, available instructions and other features . the sfdp parameters are stored in one or more parameter id entification (pid) tables. currently only one pid table is specified, but more may be added in the future. the read sfdp register instruction is com patible with the sfdp standard initially established in 2010 for pc and other applications, as well as the j edec standard jesd216 that is published in 2011 . most winbond spiflash memories shipped after june 2011 (date code 1124 and beyond) support the sfdp feature as specified in the applicable datasheet. the read sfdp instruction is initiated by driving the /c s pin low and shifting the instruction code 5ah followed by a 24 - bit address (a23 - a0) (1) into the di pin. eight dummy clocks are also required before the sfdp register contents are shifted out on the falling edge of the 40 th clk with most significant b it (msb) first as shown in figure 3 4 . for sfdp register values and descriptions, please refer to the winbond application note for sfdp definition t able. note 1: a23 - a8 = 0; a7 - a0 are used to define the starting byte address for the 256 - byte sfdp register. figure 3 4 . read sfdp register instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (5ah) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q32fv publication release date: june 03, 2016 - 68 - revision j 8.2.31 erase security registers (44h) the w 25q32fv offers three 256 - byte security registers which can be erased and programmed individually. these registers may be used by the system manufacturers to store security and other important information separately from the main memory array. the erase security register instruction is similar to the sector erase instruction . a write enable instruction must be executed before th e device will accept the erase s ecurity register instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 44 h followed by a 24 - bit address (a23 - a0) to erase one of the three security register s . addres s a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 dont care security register #2 00h 0 0 1 0 0 0 0 0 dont care security register #3 00h 0 0 1 1 0 0 0 0 dont care the erase security register instruction sequence is shown in f igure 4 5 . the /cs pin must be driven high after the eighth bit of the last byte has been l atched. if this is not done the instruction will not be executed. after /cs is dri ven high, the self - timed erase security register operation will commence for a time duratio n of t se (see ac characteristics). while the erase security register cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the erase cycle and becomes a 0 when t he cycle is finished and the device is ready to accept other instructions again. after the erase security register cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the se curity register lock bits (lb3 - 1 ) in the st atus register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, erase security register instruction to that register will be ignored (refer to section 7.1.8 for detail descriptions). figure 45 . erase security registers instruction (spi mode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (44h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q32fv - 69 - 8.2.32 program security registers (42h) the program security register instruction is similar to the page program instruction. it allows from one byte to 256 bytes of secur ity register data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the program security register instruction (status register bit wel= 1). the instruction is initiated b y driving the /cs pin low then shifting the instruction code 42h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the devi ce. address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address the program security register instruction sequence i s shown in f igure 46 . the security register lock bits (lb3 - 1 ) in the status register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, program security register instruction to that register will be ignored (see 7 .1. 8 , 8.2. 25 for detail descriptions). figure 4 6 . program security registers instruction (spi mode only) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (42h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q32fv publication release date: june 03, 2016 - 70 - revision j 8.2.33 read security registers (48h) the read security register instruction is similar to the fast re ad instruction and allows one or more data bytes to be sequen tially read from one of the three security registers. the instruction is initiated by driving the /cs pin low and then shift ing the instruction code 48h followed by a 24 - bit address (a23 - a0) an d eight dummy clocks into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the byte address is automatically incremented to the next byte address after each byte of data is shifted out . o nce the byte address reaches the last byte of the register (byte address ffh), it will reset to address 00h, the first byte of the register, and continue to increment. the instruction is completed by driving /cs high. the read security register instruction sequence is shown in f igure 4 7 . if a read security register instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read security register instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). address a23 - 16 a 15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address figure 4 7 . read security registers instruction (spi mode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (48h) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q32fv - 71 - 8.2.34 set read parameters (c0h) in qpi mode, to accommodate a wide range of applications with different needs for either maximum read frequency or minimum data access latency, set read parameters (c0h) instruction can be used to configure the number of dummy clock s for fast read (0bh) , fast read quad i/o (ebh) & burst read with wrap (0ch) instructions, and to configure the number of bytes of wrap length for the burst re ad with wrap (0ch) instruction. in standard spi mode, the set read parameters (c0h) i nstruction is not accepted. the dummy clocks for various fast read instructions in standard/dual/quad spi mode are fixed, please refer to the instruction table 1 - 2 for detail s . t he wrap length is set by w5 - 4 bit in the set burst with wrap (77h) instruc tion. this setting will remain unchanged when the device is switched from standard spi mode to qpi mode. the default wrap length after a power up or a reset instruction is 8 bytes, the default number of dummy clocks is 2. the number of dummy clocks is on ly programmable for fast read (0bh), fast read quad i/o (ebh) & burst read with wrap (0ch) instructions in the qpi mode. whenever the device is switched from spi mode to qpi mode, the number of dummy clocks should be set again, prior to any 0bh, ebh or 0ch instructions. p5 C p4 dummy clocks maximum read freq. maximum read freq. (a[1:0]=0,0) p1 C p0 wrap length 0 0 2 33mhz 33mhz 0 0 8 - byte 0 1 4 55mhz 80mhz 0 1 16 - byte 1 0 6 80mhz 104 mhz 1 0 32 - byte 1 1 8 104 mhz 104 mhz 1 1 64 - byte figure 4 8 . set read parameters instruction (qpi mode only ) /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 c0h 2 3 read parameters p4 p0 p5 p1 p6 p2 p7 p3 instruction mode 0 mode 3
w25q32fv publication release date: june 03, 2016 - 72 - revision j 8.2.35 burst read with wrap (0ch) the burst read with wrap (0ch) instruction provides an alternative way to perform the read operation with wrap around in qpi mode. the i nstruction is similar to the fast read (0bh) instruction in qpi mode, except the addressing of the read operation will wrap around to the beginning boundary of the wrap length once the ending boundary is reached. the wrap length and the number of d ummy clocks can be configured by the set read parameters (c0h) instruction. figure 4 9 . burst read with wrap instruction (qpi mode only ) dummy * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 0ch 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output * "set read parameters" instruction (c0h) can set the number of dummy clocks. byte 3 instruction
w25q32fv - 73 - 8.2.36 enter qpi mode (38h) the w 25q32fv support both standard/dual/quad serial peripheral interface (spi) and quad peripheral interface (qpi). however, spi mode and qpi mode cannot be used at the same time. enter qpi (38h) instruction is the only way to switch the device from spi mode to qpi mode. upon power - up, the default state of the devi ce upon is standard/dual/quad spi mode. this provides full backward compatibility with earlier generations of winbond serial flash memories. see instruction set t able 1 - 3 for all supported spi commands. in order to sw itch the device to qpi mode, the quad e na ble (qe) bit in status register - 2 must be set to 1 first, and an enter qpi (38h) instruction must be issued. if the quad e nable (qe) bit is 0, the enter qpi (38h) instruction will be ignored and the device will remain in spi mode. see instruction set t able 3 for all the commands supported in qpi mode. when the device is switched from spi mode to qpi mode, the existing write enable and program/erase suspend status, and the wrap length setting will remain unchanged. figure 5 0 . enter qpi instruction (spi mode only ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (38h) high impedance mode 0 mode 3
w25q32fv publication release date: june 03, 2016 - 74 - revision j 8.2.37 exit qpi mode (ffh) in order to exit the qpi mode and return to the standard/dual/quad spi mode, a n exit qpi (ffh) instruction must be issued. when the device is switched from qpi mode to spi mode, the existing write enable latch (wel) and program/erase suspend status, and the wrap length setting will remain unchanged. figure 51 . exit qpi instruction (qpi mode only ) /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 ffh instruction mode 0 mode 3
w25q32fv - 75 - 8.2.38 individual block /sector lock (36h) the individual block/sector lock provides an alternative way to protect the memory array from adverse erase/program . in order to use the individual block/sector locks, the wps bit in status register - 3 must be set to 1. if wps=0, the write protection will be determined by the combination of cmp, sec, tb, bp[2 :0] bits in the status registers . the individual block/sector lock bits are volatile bits. the default values after device power up or after a reset are 1, so the entire memory array is being protected. to lock a specific block or sect or as illustrated in figure 4d, an individual block/sector lock command must be issued by driving /cs low, shifting the instruction code 36h into the data input (di) pin on the rising edge of clk, followed by a 24 - bit address and then driving /cs high. a write enable instruction must be executed before the device will accept the individual block/sector lock instruction (status register bit wel= 1). figure 52 a. individual block /sector lock instruction (spi mode) figure 52 b. individual block /sector lock instruction (qpi mode) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 3 6 h ) h i g h i m p e d a n c e 8 9 2 9 3 0 3 1 2 4 - b i t a d d r e s s 2 3 2 2 2 1 0 * m o d e 0 m o d e 3 = m s b * / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 3 6 h i n s t r u c t i o n 2 3 4 5 2 0 1 6 1 2 8 2 1 1 7 2 2 1 8 2 3 1 9 1 3 9 1 4 1 0 1 5 1 1 a 2 3 - 1 6 6 7 4 0 5 1 6 2 7 3 a 1 5 - 8 a 7 - 0 m o d e 0 m o d e 3
w25q32fv publication release date: june 03, 2016 - 76 - revision j 8.2.39 individual block /sector unlock (39h) the individual block/sector lock provides an alternative way to protect the memory array from adverse erase/program. in order to use the individual block/sector locks, the wps bit in statu s register - 3 must be set to 1. if wps=0, the write protection will be determined by the combination of cmp, sec, tb, bp[2 :0] bits in the status registers. the individual block/sector lock bits are volatile bits. the default values after device power up or after a reset are 1, so the entire memory array is being protected. to unlock a specific block or sector as illustrated in figure 4d, an individual block/sector unlock command must be issued by driving /cs low, shifting the instruction code 39h into the data input (di) pin on the rising edge of clk, followed by a 24 - bit address and then driving /cs high. a write enable instruction must be executed before the device will accept the individual block/sector unlock instruction (status register bit wel= 1). figure 53 a. individual block unl ock instruction (spi mode) figure 53 b. i ndividual block unl ock instruction (qpi mode) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 3 9 h ) h i g h i m p e d a n c e 8 9 2 9 3 0 3 1 2 4 - b i t a d d r e s s 2 3 2 2 2 1 0 * m o d e 0 m o d e 3 = m s b * / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 3 9 h i n s t r u c t i o n 2 3 4 5 2 0 1 6 1 2 8 2 1 1 7 2 2 1 8 2 3 1 9 1 3 9 1 4 1 0 1 5 1 1 a 2 3 - 1 6 6 7 4 0 5 1 6 2 7 3 a 1 5 - 8 a 7 - 0 m o d e 0 m o d e 3
w25q32fv - 77 - 8.2.40 read block /sector lock (3 d h) the individual block/sector lock provides an alternative way to protect the memory array from advers e erase/program. in order to use the individual block/sector locks, the wps bit in status register - 3 must be set to 1. if wps=0, the write protection will be determined by the combination of cmp, sec, tb, bp[ 2 :0] bits in the status registers. the individua l block/sector lock bits are volatile bits. the default values after device power up or after a reset are 1, so the entire memory array is being protected. to read out the lock bit value of a specific block or sector as illustrated in figure 4d, a read blo ck/sector lock command must be issued by driving /cs low, shifting the instruction code 3 d h into the data input (di) pin on the rising edge of clk, followed by a 24 - bit address. the block/sector lock bit value will be shifted out on the do pin at the fal ling edge of clk with most significant bit (msb) first as shown in figure 54 . if the least significant bit (lsb) is 1, the corresponding block/sector is locked; if lsb=0, the corresponding block/sector is unlocked, erase/program operation can be performed. figure 54 a . read block lock instruction (spi mode ) figure 54 b . read block lock instruction ( qpi mode ) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 3 d h ) h i g h i m p e d a n c e 8 9 1 0 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 x x x x x x x 0 2 4 - b i t a d d r e s s 2 3 2 2 2 1 3 2 1 0 l o c k v a l u e o u t * * = m s b * m o d e 0 m o d e 3 / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 3 d h 2 3 4 5 2 0 1 6 1 2 8 2 1 1 7 2 2 1 8 2 3 1 9 1 3 9 1 4 1 0 1 5 1 1 a 2 3 - 1 6 6 7 8 9 4 0 5 1 6 2 7 3 a 1 5 - 8 a 7 - 0 l o c k v a l u e x 0 x x x x x x i o s s w i t c h f r o m i n p u t t o o u t p u t i n s t r u c t i o n m o d e 0 m o d e 3
w25q32fv publication release date: june 03, 2016 - 78 - revision j 8.2.41 global block /sector lock (7eh) all block/sector lock bits can be set to 1 by the global blo ck/sector lock instruction. the command must be issued by driving /cs low, shifting the instruction code 7eh into the data input (di) pin on the rising edge of clk, and then driving /cs high. a write enable instruction must be executed before the device will accept the global block/sector lock instruction (status register bit wel= 1). figure 55 . global block lock instruction for spi mode (left) or qpi mode (right) 8.2.42 global block /sector unlock (98h) all block/sector lock bits can be set to 0 by the glo bal block/sector unlock instruction. the command must be issued by driving /cs low, shifting the instruction code 98h into the data input (di) pin on the rising edge of clk, and then driving /cs high. a write enable instruction must be executed before th e device will accept the global block/sector unlock instruction (status register bit wel= 1). figure 56 . g lobal block unl ock instruction for spi mode (left) or qpi mode (right) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 m o d e 0 m o d e 3 i n s t r u c t i o n ( 7 e h ) h i g h i m p e d a n c e / c s c l k m o d e 0 m o d e 3 0 1 m o d e 0 m o d e 3 i o 0 i o 1 i o 2 i o 3 7 e h i n s t r u c t i o n / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 m o d e 0 m o d e 3 i n s t r u c t i o n ( 9 8 h ) h i g h i m p e d a n c e / c s c l k m o d e 0 m o d e 3 0 1 m o d e 0 m o d e 3 i o 0 i o 1 i o 2 i o 3 9 8 h i n s t r u c t i o n
w25q32fv - 79 - 8.2.43 enable reset (66h) and reset device (99h) because of the small package a nd the limitation on the number of pins, t he w 25q32fv provide a software r eset instruction instead of a dedicated reset pin. once the reset instruction is accepted, any on - going internal operations will be terminated and the device will return to its defau lt power - on state and lose all the current volatile settings, such as volatile status register bits, write enable latch (wel) status, program/erase suspend status, read parameter setting (p7 - p0), continuous read mode bit setting (m7 - m0) and wrap bit settin g (w6 - w4). enable reset (66h) and reset (99h) instructions can be issued in either spi mode or qpi mode. to avoid accidental reset, both instructions must be issued in sequen ce . any other commands other than reset (99h) after the enable reset (66h) command will disable the reset enable state. a new sequence of enable reset (66h) and reset (99h) is needed to reset the device. once the reset command is accepted by the device, the device will take approximately trst=30us to reset. during this pe riod, no command will be accepted. data corruption may happen if there is an on - going or suspended internal erase or program operation when reset command sequence is accepted by the device. it is recommended to check the busy bit and the sus bit in status register before issuing the reset command sequence. figure 5 7 a . enable reset and reset instruction sequence (spi mode) figure 5 7 b . enable reset and reset instruction sequence (qpi mode ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (99h) mode 0 mode 3 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (66h) high impedance mode 0 mode 3 0 1 99h instruction mode 0 mode 3 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 66h instruction
w25q32fv publication release date: june 03, 2016 - 80 - revision j 9. electrical character istic s 9.1 absolute maximum ratings (1) (2) parameters symbol conditions range unit supply voltage vcc C 0.6 to 4.6 v voltage applied to any pin v io relative to ground C 0.6 to vcc +0.4 v transient voltage on any pin v iot <20ns transient relative to ground C 2 .0v to vcc+ 2 .0v v storage temperature t stg C 65 to +150 c lead temperature t lead ( 3 ) see note ( 3 ) c electrostatic discharge voltage v esd ( 2 ) human body model C 2000 to +2000 v notes: 1.this device has been designed and tested for the specified operation ranges. prope r operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyond absolute maximum ratings may cause permanent damage. 2. jedec std jesd22 - a114a (c1=100pf, r1=1500 ohms, r2=500 ohms). 3.compliant with jedec standard j - std - 20c for small body sn - pb or pb - free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 9.2 operating ranges parameter symbol conditions spec unit min max supply voltage vcc (1) f r = 104 mhz, f r = 50 mhz 2.7 3.6 v ambient temperature, operating t a industrial C 40 +85 c note: 1. vcc voltage during read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage.
w25q32fv - 81 - 9.3 p ower - u p power - down timing and requirements ( 1 ) parameter symbol spec unit min max vcc (min) to /cs low t vsl 20 s time delay before write instruction t puw 5 ms write inhibit threshold voltage v wi 1.0 2.0 v note : 1. these parameters are charact erized only. figure 58 a . power - up timing and voltage levels figure 58 b. power - up, power - down requirement vcc tvsl read instructions allowed device is fully accessible tpuw /cs must track vcc program, erase and write instructions are ignored reset state vcc (max) vcc (min) v wi time vcc time / cs must track vcc during vcc ramp up / down / cs
w25q32fv publication release date: june 03, 2016 - 82 - revision j 9.4 dc electrical characteristics parameter symbol conditions spec unit min typ max inpu t capacitance c in ( 1 ) v in = 0v 6 pf output capacitance cout ( 1 ) v out = 0v 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 10 50 a power - down current i cc 2 /cs = vcc, vin = gnd or vcc 1 20 a current read data / dual /quad 50mhz i cc 3 ( 2 ) c = 0.1 vcc / 0.9 vcc do = open 15 ma current read data / dual /quad 80mhz i cc 3 ( 2 ) c = 0.1 vcc / 0.9 vcc do = open 18 ma current read data / dual output read /quad output read 104mhz i cc 3 ( 2 ) c = 0.1 vcc / 0.9 vcc do = open 20 ma current write status register i cc 4 /cs = vcc 8 12 ma current page program i cc 5 /cs = vcc 20 25 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low vo ltage v il C 0.5 vcc x 0.3 v input high voltage v ih vcc x 0.7 vcc + 0.4 v output low voltage v ol i ol = 100 a 0.2 v output high voltage v oh i oh = C 100 a vcc C 0.2 v notes: 1 . tested on sample basis and specified through design and characteriza tion data. ta = 25 c, vcc = 3.0 v , 25 % driver strength 2 . checker board pattern.
w25q32fv - 83 - 9.5 ac measurement conditions ( 1 ) parameter symbol spec unit min max load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0. 1 vcc to 0. 9 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0. 5 vcc to 0. 5 vcc v note: 1. output hi - z is defined as the point where data out is no longer driven. figure 5 9 . ac m easurement i/o waveform input and output timing reference levels input levels 0.9 vcc 0.1 vcc 0.5 vcc
w25q32fv publication release date: june 03, 2016 - 84 - revision j 9.6 ac electrical characteristics (6) description symbol alt spec unit min typ max clock frequency for all other instructions 2.7v - 3.6 v vcc & industrial temperature . except read data instructions (03h) f r f c1 d.c. 104 mhz cloc k frequency for read data instruction ( 03h ) f r f c 2 d.c. 50 mhz clock high, low time for all instructions except for read data (03h) t clh , t cll ( 1) 4 ns clock high, low time for read data (03h) instruction t crlh , t crll ( 1) 8 ns clock rise time peak to peak t clch ( 2) 0.1 v/ns clock fall time peak to peak t chcl ( 2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 3 ns /cs active hold time relative to clk t chsh 3 ns /cs not active setup time relative to clk t shch 3 ns /cs deselect time t shsl t csh 50 ns output disable time t shqz ( 2) t dis 7 ns clock low to output valid t clqv t v 7 ns output hold time t clqx t ho 2 ns /hold active setup time relative to clk t hlch 5 ns /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns c ontinued C next page ac electrical characteristics ( contd)
w25q32fv - 85 - ac electrical characteristics (contd) description symbol alt spec unit min typ max /hold to output low - z t hhqx ( 2) t lz 7 ns /hold to output high - z t hlqz ( 2) t hz 12 ns write protect set up time before /cs low t whsl ( 3) 20 ns write protect hold time after /cs high t shwl ( 3) 100 ns /cs high to power - down mode t dp ( 2) 3 s /cs high to standby mode without id read t res 1 ( 2) 3 s /cs high to standby mode with id read t res 2 ( 2) 1 .8 s /cs high to next instruction after suspend t sus ( 2) 20 s /cs high to next instruction after reset t sus ( 2) 30 s /reset pin low period to reset the device t r s t ( 2) (5) 1 s write status register time t w 10 15 ms byte program time (first byte) t bp1 (4 ) 30 50 s additional byte program time (after first byte) t bp2 (4 ) 2.5 12 s page program time t pp 0.7 3 ms sector erase time ( 4kb) w 25q 32 fvxxig t se 100 400 ms w25q 32 fvxxiq w25q 32 fvxxi f 45 block erase time ( 32 kb) t be 1 120 1,6 00 ms block erase time (64kb) t be 2 150 2 ,000 ms chip erase time t ce 10 5 0 s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characterization, not 100% tested in production. 3. only appli cable as a constraint for a write status register instruction when srp[1:0]=(0,1) . 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed. 5. it s possible to reset the device with shorter t reset (as short as a few hundred ns), a 1us minimum is recommended to ensure reliable operation. 6. 4 - bytes address alignment for qpi/quad read
w25q32fv publication release date: june 03, 2016 - 86 - revision j 9.7 serial output timing 9.8 serial input timing 9.9 /hold timing 9.10 /wp timing /cs clk io output tclqx tclqv tclqx tclqv tshqz tcll lsb out tclh msb out /cs clk io input tchsl msb in tslch tdvch tchdx tshch tchsh tclch tchcl lsb in tshsl /cs clk io output /hold tchhl thlch tchhh thhch thlqz thhqx io input /cs clk /wp twhsl tshwl io input write status register is allowed write status register is not allowed
w25q32fv - 87 - 10. package specificatio n s 10.1 8 - p in soic 208 - mil (package code s s ) symbol millimeters inches min nom max min nom max a 1.75 1.95 2.16 0.069 0.077 0.085 a1 0.05 0.15 0.25 0.002 0.006 0.010 a2 1.70 1.80 1.91 0.067 0.071 0.075 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.19 0.20 0.25 0.007 0.008 0.010 d 5.18 5.28 5.38 0.204 0.208 0.212 d1 5.13 5.23 5.33 0.202 0.206 0.210 e 5.18 5.28 5.38 0.204 0.208 0.212 e1 5.13 5.23 5.33 0.202 0.206 0.210 e 1.27 bsc 0.050 bsc h 7.70 7.90 8.10 0.303 0.311 0.319 l 0.50 0.65 0.80 0.020 0.026 0.031 y --- --- 0.10 --- --- 0.004 0 --- 8 0 --- 8
w25q32fv publication release date: june 03, 2016 - 88 - revision j 10.2 8 - pin vsop 208 - mil (package code st ) symbol millimeters inches min nom max min nom max a D D 1.00 D D 0.03 9 a1 0.05 0.10 0.15 0.00 2 0.00 4 0.00 6 a2 0.75 0.80 0.85 0.0 3 0 0.0 3 1 0.0 33 b 0.35 0.42 0.48 0.0 14 0.01 7 0.0 19 c 0. 127 ref 0.00 5 ref d 5.18 5.28 5.38 0. 204 0. 208 0. 212 e 7.70 7.90 8.10 0. 303 0. 311 0. 319 e 1 5.18 5.28 5.38 0. 204 0.208 0.212 e D 1.27 D D 0.0 5 0 D l 0.50 0. 65 0. 8 0 0.0 20 0.0 2 6 0.0 31 y D D 0. 10 D D 0.00 4 0 D 8 0 D 8
w25q32fv - 89 - 10.3 8 - pad wson 6x5 - mm (package code z p) symbol millimeters inches min nom max min nom ma x a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.35 0.40 0.48 0.014 0.016 0.019 c --- 0.20 ref --- --- 0.0 08 ref --- d 5.90 6.00 6.10 0.232 0.236 0.240 d2 3.35 3.40 3.45 0.132 0.134 0.136 e 4.90 5.00 5.10 0.193 0.197 0.20 1 e2 4.25 4.30 4.35 0.167 0.169 0.171 e 1.27 bsc 0.050 bsc l 0.55 0.60 0.65 0.022 0.024 0.026 y 0.00 --- 0.075 0.000 --- 0.003 note: 1. the metal pad area on the bottom center of the package is not connected to any internal electrical signals. it ca n be left floating or connected to t he device ground (gnd pin). avoid placement of exposed pcb vias under the pad .
w25q32fv publication release date: june 03, 2016 - 90 - revision j 10.4 8 - pad wson 8x6 - mm (package code z e) symbol millimeters inches min nom max min nom max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.35 0.40 0.48 0.014 0.016 0.019 c --- 0.20 ref --- --- 0.008 ref --- d 7.90 8.00 8.10 0.311 0.315 0.319 d2 3.35 3.40 3.45 0.1 32 0.1 34 0.1 36 e 5.90 6.00 6.10 0.232 0.236 0.240 e2 4.25 4.30 4.35 0. 167 0. 169 0. 171 e --- 1 .27 --- --- 0. 050 --- l 0.45 0.50 0.55 0.018 0.020 0.022 y 0.00 --- 0.050 0.000 --- 0.002 note: 1. the metal pad area on the bottom center of the package is not connected to any internal electrical signals. it can be left floating or connected to t he device ground (gnd pin). avoid placement of exposed pcb vias under the pad .
w25q32fv - 91 - 10.5 16 - pin soic 300 - mil (package code s f) symbol millimeters inches min nom max min nom max a 2.36 2.49 2.64 0.093 0.098 0.104 a1 0.10 --- 0.30 0.004 --- 0.012 a2 --- 2.31 - -- --- 0.091 --- b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.18 0.23 0.28 0.007 0.009 0.011 d 10.08 10.31 10.49 0.397 0.406 0.413 e 10.01 10.31 10.64 0.394 0.406 0.419 e1 7.39 7.49 7.59 0.291 0.295 0.299 e 1.27 bsc 0.050 bsc l 0.38 0.81 1.27 0.015 0.032 0.050 y --- --- 0.076 --- --- 0.003 0 --- 8 0 --- 8
w25q32fv publication release date: june 03, 2016 - 92 - revision j 10.6 8 - pin pdip 300 - mil (package code da) symbol millimeters inches min nom max min nom max a --- --- 5.33 --- --- 0.210 a1 0.38 --- --- 0.015 --- --- a2 3.18 3.30 3.43 0.125 0.130 0.135 d 9.02 9.27 10.16 0.355 0.365 0.400 e 7.62 bsc 0.300 bsc e1 6.22 6.35 6.48 0.245 0.250 0.255 l 2.92 3.30 3.81 0.115 0.130 0.150 e b 8.51 9.02 9.53 0.335 0.355 0.375 ? 0 7 15 0 7 15 d --- 2.54 --- --- 0.100 --- w --- 1.52 --- --- 0.060 --- p --- 0.46 --- --- 0.018 --- d w p
w25q32fv - 93 - 10.7 24 - ba ll tfbga 8x6 - m m (package cod e t b, 5x5 - 1 ball array ) symbol millimeters inches min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.25 0.30 0.35 0.01 0 0.0 12 0.0 14 a2 --- 0.85 --- --- 0.033 --- b 0.35 0.40 0.45 0.014 0.0 16 0.0 18 d 7.90 8.00 8.10 0 .311 0.31 5 0.31 9 d 1 4.00 bsc 0.157 bsc e 5.90 6.00 6.10 0.232 0.236 0.240 e 1 4.00 bsc 0.157 bsc se 1.00 typ 0.039 typ sd 1.00 typ 0.039 typ e 1.00 bsc 0.039 bsc note: ball land: 0.45mm. ball opening: 0.35mm pcb ball land suggested <= 0.35mm
w25q32fv publication release date: june 03, 2016 - 94 - revision j 10.8 24 - ball tfbga 8x6 - m m (package cod e t c, 6x4 ball array ) symbol millimeters inches min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.25 0.30 0.35 0.01 0 0.0 12 0.0 14 b 0.35 0.40 0.45 0.014 0.0 16 0.0 18 d 7.95 8.00 8.05 0 .313 0.31 5 0.31 7 d 1 5.00 bsc 0.197 bsc e 5.95 6.00 6.05 0.234 0.236 0.238 e 1 3.00 bsc 0.118 bsc e 1.00 bsc 0.039 bsc note: ball land: 0.45mm. ball opening: 0.35mm pcb ball land suggested <= 0.35mm
w25q32fv - 95 - 11. ordering information notes: 1. the w prefix is not included on the part marking. 2. only the 2 nd letter is used for the part marking; wson package type zp & ze are not used for the part marking. 3. standar d bulk shipments are in tube (shape e). please specify alternate packing method, such as tape and reel (shape t) or tray (shape s), when placing orders. 4. for shipments p with otp feature enabled, please contact winbond. w (1) 25q 32f v xx (2) i w = winbond 25 q = s pi flash serial flash memory with 4 kb sectors, du al /quad i/o 32f = 32m - bit v = 2.7v to 3.6v ss = 8 - pin soic 208 - mil st = 8 - pin vsop 208 - mil sf = 16 - pin soic 300 - mil da = 8 - pin pdip 300 - mil zp = wson8 6x5 - mm ze = wson8 8x6 - mm tb = tfbga 8x6 - mm (5x5 - 1 ball array) tc = tfbga 8x6 - mm (6x4 ball array) i = industrial ( - 40 c to +85c) ( 3,4 ) g = green package (lead - free, rohs compliant, halogen - free (tbba), antimony - oxide - free sb 2 o 3 ) f = green package with fast sector erase time (tse) q = green package w ith qe=1 in status register - 2
w25q32fv publication release date: june 03, 2016 - 96 - revision j 11.1 valid pa rt numbers and top si de marking the following table provides the valid part numbers for the w 25q32fv spiflash memory . please contact winbond for specific availability by density and package type. winbond spiflash memories use a 1 2 - digit product number for ordering. however, d ue to limited space, the top side marking on all packages uses an abbreviated 10 - digit number. package type density product number top side marking s s soic - 8 208 - mil 32m - bit w 25q32fv s s ig w 25q32fvss i q w 25q32fvssi f 25q32fv s i g 25q3 2fvsiq 25q32fvsi f st (1) vsop - 8 208 - mil 32m - bit w 25q32fvst ig w 25q32fvsti f 25q32fvti g 25q32fvti f s f soic - 16 300 - mil 32m - bit w 25q32fv s fig w 25q32fvsf i q w 25q32fvsfi f 25q32fv f i g 25q32fvfiq 25q32fv f i f da pdip - 8 300 - mil 32m - bit w 25q32fvda ig w 25q32fvda i q w 25q32fvdai f 25q32fvai g 25q32fvaiq 25q32fvai f zp wson - 8 6 x 5 - mm 32m - bit w 25q32fvzp ig w 25q32fvzp i q w 25q32fvzp i f 25q32fvi g 25q32fviq 25q32fvi f z e wson - 8 8x6 - mm 32m - bit w 25q32fvz eig w 25q32fvz ei f 25q32fvi g 25q32fvi f t b (1) tfbga - 24 8x6 - mm (5x5 ball array) 32m - bit w 25q32fvt big w 25q32fvtbi f 25q32fv b i g 25q32fv b i f t c (1) tfbga - 24 8x6 - mm (6x4 ball array) 3 2m - bit w 25q32fvt cig w 25q32fvt ci f 25q32fv c i g 25q32fv c i f note: 1. these package types are special order, please contact winbond for more information .
w25q32fv - 97 - 12. revision history version date page description a 0 9 / 27 /2011 new create preliminary b 0 4 / 13 /2012 10, 14, 84 66 84 89 94 - 95 updated reset descriptions referred to sfdp definition application note updated erase time updated wson metal pad size added q order option c 07/ 20 /2012 all 19, 84 10, 15, 80 95 removed preliminary designator updated default driver s trength setting added power - down requirement updated pdip part number and marking d 10/ 15 /2012 80 91 95 updated power - up timing parameters updated pdip dimensions updated ordering part number d1 01/25/2013 8, 1 5 added rest pin description of soic - 16 300 - mil e 03/1 5 /2013 9 2 103,104 modified the tse of w25q32fvxxiq e1 03/ 29 /2013 84 94,95 added the tse of w25q32fvxxi f added w25q 32 fvxxif into order information f 04/13/2013 84 modified the tse of w25q32fvxxiq & if g 04/29/2013 18 19 80 89,90 added quad ena ble default description a dded drv default setting value modified supply voltage updated note for metal pad for wson, uson h 09/16/2013 63 - 64 80 - 85 modified the description of 92h, 94h modified the description of dc/ac table i 10/20/2015 70 modified the t ypo of security register number j 06/0 3 /2016 96 removed ip part no.
w25q32fv publication release date: june 03, 2016 - 98 - revision j trademarks winbond and s piflash are trademarks of winbond electronics corporation . all other marks are the property of their respective owner. important notice winbon d products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signa l instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore , winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein pe rsonal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such imp roper use or sales. information in this document is provided solely in connection with winbond products. winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice.

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